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Verilog Simulation

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rtl_tb_test.yml
19 workflow runs
19 workflow runs

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Added cocotb testbench for DFF_reg Verilog Simulation #19: Commit 1ed3cb1 pushed by jxwleong
September 8, 2023 05:35 21s master
master
September 8, 2023 05:35 21s
Added cocotb testbench for mux4to1 Verilog Simulation #18: Commit 06ea9be pushed by jxwleong
September 8, 2023 04:41 31s master
master
September 8, 2023 04:41 31s
Added better naming for test functions Verilog Simulation #17: Commit 75e2754 pushed by jxwleong
September 8, 2023 03:28 19s master
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September 8, 2023 03:28 19s
Fixed Makefile which causes the build fail due to path changes Verilog Simulation #16: Commit 1e490c3 pushed by jxwleong
September 8, 2023 03:20 23s master
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September 8, 2023 03:20 23s
Moved cocotb Makefile into testbench/cocotb Verilog Simulation #15: Commit 4acd3f1 pushed by jxwleong
September 8, 2023 03:16 24s master
master
September 8, 2023 03:16 24s
Added paths-ignore for the github workflow files Verilog Simulation #14: Commit da00715 pushed by jxwleong
September 8, 2023 03:15 21s master
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September 8, 2023 03:15 21s
Renamed 'makefile'=>'Makefile' Verilog Simulation #13: Commit 3777a13 pushed by jxwleong
September 8, 2023 03:10 21s master
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September 8, 2023 03:10 21s
Added some print statements for rtl_tb Verilog Simulation #12: Commit ce6e70e pushed by jxwleong
September 7, 2023 11:34 19s master
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September 7, 2023 11:34 19s
Moved unused verilog file to archive Verilog Simulation #11: Commit 35789f7 pushed by jxwleong
September 7, 2023 08:29 17s master
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September 7, 2023 08:29 17s
Fixed some typo in README Verilog Simulation #10: Commit abbd50c pushed by jxwleong
September 7, 2023 08:27 19s master
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September 7, 2023 08:27 19s
Rename new status badge for Verilog Simulation Verilog Simulation #9: Commit 00c1da3 pushed by jxwleong
September 7, 2023 08:18 17s master
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September 7, 2023 08:18 17s
Added new status badge for Verilog Simulation Verilog Simulation #8: Commit 435c2fb pushed by jxwleong
September 7, 2023 08:15 33s master
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September 7, 2023 08:15 33s
Attemp #6 to fix the github action, renamed Makefile=>makefile Verilog Simulation #7: Commit ee28e38 pushed by jxwleong
September 7, 2023 08:12 20s master
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September 7, 2023 08:12 20s
Attemp #5 to fix the github action Verilog Simulation #6: Commit c44e88a pushed by jxwleong
September 7, 2023 08:09 19s master
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September 7, 2023 08:09 19s
Attemp #4 to fix the github action Verilog Simulation #5: Commit 61bb229 pushed by jxwleong
September 7, 2023 08:06 Failure master
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September 7, 2023 08:06 Failure
Attemp #3 to fix the github action Verilog Simulation #4: Commit 403dffa pushed by jxwleong
September 7, 2023 08:03 Failure master
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September 7, 2023 08:03 Failure
Attempt #2 to fix the github workflow Verilog Simulation #3: Commit 59f2787 pushed by jxwleong
September 7, 2023 07:59 Failure master
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September 7, 2023 07:59 Failure
Fixed workflow for rtl_tb simulation Verilog Simulation #2: Commit bf34f9f pushed by jxwleong
September 7, 2023 07:57 17s master
master
September 7, 2023 07:57 17s
Added github workflow for rtl_tb simulation Verilog Simulation #1: Commit 750620b pushed by jxwleong
September 7, 2023 07:54 18s master
master
September 7, 2023 07:54 18s