Added github workflow for rtl_tb simulation #1
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| name: Run Verilog Simulation | |
| on: | |
| push: | |
| branches: | |
| - master | |
| pull_request: | |
| branches: | |
| - master | |
| jobs: | |
| build: | |
| runs-on: ubuntu-latest | |
| steps: | |
| - name: Checkout code | |
| uses: actions/checkout@v2 | |
| - name: Set up Icarus Verilog | |
| run: sudo apt-get -y install iverilog | |
| - name: Build and run Verilog simulation | |
| run: make -C testbench/rtl_tb -f Makefile all | |
| - name: Clean up | |
| run: make -C testbench/rtl_tb -f Makefile clean |