Renamed 'makefile'=>'Makefile' #13

	name: Verilog Simulation

	on:
	push:
	branches:
	- master
	pull_request:
	branches:
	- master

	jobs:
	build:
	runs-on: ubuntu-latest

	steps:
	- name: Checkout code
	uses: actions/checkout@v2

	- name: Set up Icarus Verilog
	run: sudo apt-get -y install iverilog

	- name: Build and run Verilog simulation
	working-directory: testbench/rtl_tb # Subsequent step will back to root directory automatically
	run:
	make -f Makefile all


	- name: Clean up
	working-directory: testbench/rtl_tb
	run:
	make -f Makefile clean

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