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Added new status badge for Verilog Simulation Cocotb Test #24: Commit 435c2fb pushed by jxwleong
September 7, 2023 08:15 50s master
master
September 7, 2023 08:15 50s
Added new status badge for Verilog Simulation Verilog Simulation #8: Commit 435c2fb pushed by jxwleong
September 7, 2023 08:15 33s master
master
September 7, 2023 08:15 33s
Attemp #6 to fix the github action, renamed Makefile=>makefile Cocotb Test #23: Commit ee28e38 pushed by jxwleong
September 7, 2023 08:12 44s master
master
September 7, 2023 08:12 44s
Attemp #6 to fix the github action, renamed Makefile=>makefile Verilog Simulation #7: Commit ee28e38 pushed by jxwleong
September 7, 2023 08:12 20s master
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September 7, 2023 08:12 20s
Attemp #5 to fix the github action Verilog Simulation #6: Commit c44e88a pushed by jxwleong
September 7, 2023 08:09 19s master
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September 7, 2023 08:09 19s
Attemp #5 to fix the github action Cocotb Test #22: Commit c44e88a pushed by jxwleong
September 7, 2023 08:09 54s master
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September 7, 2023 08:09 54s
Attemp #4 to fix the github action Cocotb Test #21: Commit 61bb229 pushed by jxwleong
September 7, 2023 08:06 35s master
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September 7, 2023 08:06 35s
Attemp #4 to fix the github action Verilog Simulation #5: Commit 61bb229 pushed by jxwleong
September 7, 2023 08:06 Failure master
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September 7, 2023 08:06 Failure
Attemp #3 to fix the github action Cocotb Test #20: Commit 403dffa pushed by jxwleong
September 7, 2023 08:03 38s master
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September 7, 2023 08:03 38s
Attemp #3 to fix the github action Verilog Simulation #4: Commit 403dffa pushed by jxwleong
September 7, 2023 08:03 Failure master
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September 7, 2023 08:03 Failure
Attempt #2 to fix the github workflow Cocotb Test #19: Commit 59f2787 pushed by jxwleong
September 7, 2023 07:59 47s master
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September 7, 2023 07:59 47s
Attempt #2 to fix the github workflow Verilog Simulation #3: Commit 59f2787 pushed by jxwleong
September 7, 2023 07:59 Failure master
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September 7, 2023 07:59 Failure
Fixed workflow for rtl_tb simulation Verilog Simulation #2: Commit bf34f9f pushed by jxwleong
September 7, 2023 07:57 17s master
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September 7, 2023 07:57 17s
Fixed workflow for rtl_tb simulation Cocotb Test #18: Commit bf34f9f pushed by jxwleong
September 7, 2023 07:57 35s master
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September 7, 2023 07:57 35s
Added github workflow for rtl_tb simulation Verilog Simulation #1: Commit 750620b pushed by jxwleong
September 7, 2023 07:54 18s master
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September 7, 2023 07:54 18s
Added github workflow for rtl_tb simulation Cocotb Test #17: Commit 750620b pushed by jxwleong
September 7, 2023 07:54 40s master
master
September 7, 2023 07:54 40s
Crate makefile to compile and run the rtl_tb testbenches Cocotb Test #16: Commit 0d9dfee pushed by jxwleong
September 7, 2023 07:49 40s master
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September 7, 2023 07:49 40s
Added db and incremental_db in .gitignore Cocotb Test #15: Commit a534a1d pushed by jxwleong
September 7, 2023 07:01 43s master
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September 7, 2023 07:01 43s
Moved testbenches written in verilog to testbench/rtl_tb/ Cocotb Test #14: Commit d7b2e7c pushed by jxwleong
September 7, 2023 06:58 35s master
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September 7, 2023 06:58 35s
Added .idea in .gitignore Cocotb Test #13: Commit c3cacc9 pushed by jxwleong
September 7, 2023 06:57 43s master
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September 7, 2023 06:57 43s
Moved unused_module into /rtl folder Cocotb Test #12: Commit 6d24efd pushed by jxwleong
September 7, 2023 06:55 52s master
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September 7, 2023 06:55 52s
Moved the RTL code into /rtl folder Cocotb Test #11: Commit c92159d pushed by jxwleong
September 7, 2023 06:53 50s master
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September 7, 2023 06:53 50s
Renamed test folder to testbench for clarity Cocotb Test #10: Commit a80073e pushed by jxwleong
September 7, 2023 06:49 51s master
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September 7, 2023 06:49 51s
Cleanup test_mux2to1.py Cocotb Test #9: Commit 7998b0e pushed by jxwleong
September 7, 2023 05:49 39s master
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September 7, 2023 05:49 39s
Fixed error in makefile where the iverlog complain can't find source … Cocotb Test #8: Commit 18f53f4 pushed by jxwleong
September 7, 2023 05:31 48s master
master
September 7, 2023 05:31 48s