Moved the RTL code into /rtl folder

jxwleong · Sep 7, 2023 · c92159d · c92159d
1 parent a80073e
commit c92159d
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Showing 10 changed files with 10 additions and 10 deletions.
diff --git a/makefile b/makefile
@@ -1,6 +1,6 @@
 # Makefile
 THIS_DIR := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
-
+RTL_DIR := $(THIS_DIR)/rtl
 
 # defaults
 SIM ?= icarus
@@ -22,15 +22,15 @@ all:	test_microprocessor  \
 # MODULE is the basename of the Python test file
 # use VHDL_SOURCES instead VERILOG_SOURCES of for VHDL files
 #Paths to HDL source files
-VERILOG_SOURCES	+= $(THIS_DIR)/CombinedCUnDP.v
-VERILOG_SOURCES += $(THIS_DIR)/CU.v
-VERILOG_SOURCES += $(THIS_DIR)/DP.v
-
-VERILOG_SOURCES += $(THIS_DIR)/DFF_reg.v
-VERILOG_SOURCES += $(THIS_DIR)/RAM.v
-VERILOG_SOURCES += $(THIS_DIR)/addSubstractor.v
-VERILOG_SOURCES += $(THIS_DIR)/mux2to1.v
-VERILOG_SOURCES += $(THIS_DIR)/mux4to1.v
+VERILOG_SOURCES	+= $(RTL_DIR)/CombinedCUnDP.v
+VERILOG_SOURCES += $(RTL_DIR)/CU.v
+VERILOG_SOURCES += $(RTL_DIR)/DP.v
+
+VERILOG_SOURCES += $(RTL_DIR)/DFF_reg.v
+VERILOG_SOURCES += $(RTL_DIR)/RAM.v
+VERILOG_SOURCES += $(RTL_DIR)/addSubstractor.v
+VERILOG_SOURCES += $(RTL_DIR)/mux2to1.v
+VERILOG_SOURCES += $(RTL_DIR)/mux4to1.v
 
 
 test_microprocessor:

diff --git a/AlteraDE1_SimpleProcessor.v → rtl/AlteraDE1_SimpleProcessor.v b/AlteraDE1_SimpleProcessor.v → rtl/AlteraDE1_SimpleProcessor.v
diff --git a/CU.v → rtl/CU.v b/CU.v → rtl/CU.v
diff --git a/CombinedCUnDP.v → rtl/CombinedCUnDP.v b/CombinedCUnDP.v → rtl/CombinedCUnDP.v
diff --git a/DFF_reg.v → rtl/DFF_reg.v b/DFF_reg.v → rtl/DFF_reg.v
diff --git a/DP.v → rtl/DP.v b/DP.v → rtl/DP.v
diff --git a/RAM.v → rtl/RAM.v b/RAM.v → rtl/RAM.v
diff --git a/addSubstractor.v → rtl/addSubstractor.v b/addSubstractor.v → rtl/addSubstractor.v
diff --git a/mux2to1.v → rtl/mux2to1.v b/mux2to1.v → rtl/mux2to1.v
diff --git a/mux4to1.v → rtl/mux4to1.v b/mux4to1.v → rtl/mux4to1.v