Skip to content
This repository has been archived by the owner on Aug 27, 2019. It is now read-only.

Commit

Permalink
nscscc: add debug port
Browse files Browse the repository at this point in the history
  • Loading branch information
name1e5s committed Aug 13, 2019
1 parent 6a67e26 commit c88f126
Showing 1 changed file with 7 additions and 1 deletion.
8 changes: 7 additions & 1 deletion mycpu_top.v
Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,13 @@ module mycpu_top(
input [3 :0] bid ,
input [1 :0] bresp ,
input bvalid ,
output bready
output bready,

// Debug port
output [31:0] debug_wb_pc,
output [3:0] debug_wb_rf_wen,
output [4:0] debug_wb_rf_wnum,
output [31:0] debug_wb_rf_wdata
);

wire ien, iok, iok1, iok2, den, dok;
Expand Down

0 comments on commit c88f126

Please sign in to comment.