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nscscc: fix error
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@name1e5s
name1e5s committed Aug 13, 2019
1 parent b0cc357 commit 6a67e26
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Showing 5 changed files with 93 additions and 8 deletions.
2 changes: 1 addition & 1 deletion cp0.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ module cp0(

// TLB...
input miss_probe,
input [3:0] matched_index_probe,
input [2:0] matched_index_probe,
output logic user_mode,
output logic cp0_kseg0_uncached,
output logic [7:0] curr_ASID,
Expand Down
41 changes: 39 additions & 2 deletions mmu_map_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,14 @@ module mmu_map_top(
output logic inst_illegal_2,
output logic inst_tlb_invalid_2,

input [31:0] iaddr_3,
input inst_en_3,
output logic [31:0] iaddr_psy_3,
output logic inst_uncached_3,
output logic inst_miss_3,
output logic inst_illegal_3,
output logic inst_tlb_invalid_3,

input [31:0] daddr,
input data_en,
output logic [31:0] daddr_psy,
Expand All @@ -46,8 +54,8 @@ module mmu_map_top(
input user_mode,
input cp0_kseg0_uncached,
input [7:0] curr_ASID,
input [3:0] cp0_index,
input [3:0] cp0_random,
input [2:0] cp0_index,
input [2:0] cp0_random,
input [85:0] cp0_tlb_conf_in,
output logic [85:0] cp0_tlb_conf_out
);
Expand All @@ -56,20 +64,24 @@ module mmu_map_top(
wire [31:0] ipaddr_direct;
wire [31:0] ipaddr_direct_1;
wire [31:0] ipaddr_direct_2;
wire [31:0] ipaddr_direct_3;
wire [31:0] dpaddr_direct;
wire [31:0] ipaddr_tlb;
wire [31:0] ipaddr_tlb_1;
wire [31:0] ipaddr_tlb_2;
wire [31:0] ipaddr_tlb_3;
wire [31:0] dpaddr_tlb;

wire iaddr_uncached_direct;
wire iaddr_uncached_direct_1;
wire iaddr_uncached_direct_2;
wire iaddr_uncached_direct_3;
wire daddr_uncached_direct;

wire iaddr_in_tlb;
wire iaddr_in_tlb_1;
wire iaddr_in_tlb_2;
wire iaddr_in_tlb_3;
wire daddr_in_tlb;

logic miss_inst;
Expand All @@ -81,6 +93,9 @@ module mmu_map_top(
logic miss_inst_2;
logic valid_inst_2;
logic uncached_inst_2;
logic miss_inst_3;
logic valid_inst_3;
logic uncached_inst_3;

logic miss_data;
logic valid_data;
Expand All @@ -99,6 +114,10 @@ module mmu_map_top(
assign inst_uncached_2 = iaddr_in_tlb_2 ? uncached_inst_2 : iaddr_uncached_direct_2;
assign inst_miss_2 = iaddr_in_tlb_2 && miss_inst_2;
assign inst_tlb_invalid_2 = iaddr_in_tlb_2 && ~valid_inst_2;
assign iaddr_psy_3 = iaddr_in_tlb_3 ? ipaddr_tlb_3 : ipaddr_direct_3;
assign inst_uncached_3 = iaddr_in_tlb_3 ? uncached_inst_3 : iaddr_uncached_direct_3;
assign inst_miss_3 = iaddr_in_tlb_3 && miss_inst_3;
assign inst_tlb_invalid_3 = iaddr_in_tlb_3 && ~valid_inst_3;

assign daddr_psy = daddr_in_tlb ? dpaddr_tlb : dpaddr_direct;
assign data_uncached = daddr_in_tlb ? uncached_data : daddr_uncached_direct;
Expand Down Expand Up @@ -145,6 +164,19 @@ module mmu_map_top(
.addr_in_tlb (iaddr_in_tlb_2)
);

mmu_map mmu_map_inst_3(
.clk (clk),
.rst (rst),
.en (inst_en_3),
.vaddr (iaddr_3),
.user_mode (user_mode),
.cp0_kseg0_uncached (cp0_kseg0_uncached),
.paddr (ipaddr_direct_3),
.addr_invalid (inst_illegal_3),
.addr_uncached (iaddr_uncached_direct_3),
.addr_in_tlb (iaddr_in_tlb_3)
);

mmu_map mmu_map_data(
.clk (clk),
.rst (rst),
Expand Down Expand Up @@ -180,6 +212,11 @@ module mmu_map_top(
.miss_inst_2 (miss_inst_2),
.valid_inst_2 (valid_inst_2),
.uncached_inst_2 (uncached_inst_2),
.vaddr_inst_3 (iaddr_3),
.paddr_inst_3 (ipaddr_tlb_3),
.miss_inst_3 (miss_inst_3),
.valid_inst_3 (valid_inst_3),
.uncached_inst_3 (uncached_inst_3),
.vaddr_data (daddr),
.paddr_data (dpaddr_tlb),
.miss_data (miss_data),
Expand Down
16 changes: 11 additions & 5 deletions pc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,12 @@ module pc(
input pc_tlb_invalid_seq1,
input pc_tlb_uncached_seq1,

input [31:0] pc_address_psy_next_seq2,
input pc_tlb_miss_seq2,
input pc_tlb_illegal_seq2,
input pc_tlb_invalid_seq2,
input pc_tlb_uncached_seq2,

output logic [31:0] pc_address,
output logic [31:0] pc_address_psy,
output logic tlb_miss,
Expand Down Expand Up @@ -77,11 +83,11 @@ module pc(
else if(pc_en) begin
if(exception_taken) begin
pc_address_next = exception_address;
pc_address_psy_next = { 3'd0, exception_address[28:0] };
pc_tlb_miss_next = 1'd0;
pc_tlb_illegal_next = 1'd0;
pc_tlb_invalid_next = 1'd0;
pc_tlb_uncached_next= exception_address[29];
pc_address_psy_next = pc_address_psy_next_seq2;
pc_tlb_miss_next = pc_tlb_miss_seq2;
pc_tlb_illegal_next = pc_tlb_illegal_seq2;
pc_tlb_invalid_next = pc_tlb_invalid_seq2;
pc_tlb_uncached_next= pc_tlb_uncached_seq2;
end
else if(branch_en && branch_taken) begin
pc_address_next = branch_address;
Expand Down
20 changes: 20 additions & 0 deletions sirius.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -363,6 +363,12 @@ module sirius(
wire pc_tlb_invalid_seq1;
wire pc_tlb_uncached_seq1;

wire [31:0] pc_address_psy_next_seq2;
wire pc_tlb_miss_seq2;
wire pc_tlb_illegal_seq2;
wire pc_tlb_invalid_seq2;
wire pc_tlb_uncached_seq2;

pc pc_0(
.clk (clk),
.rst (rst),
Expand Down Expand Up @@ -396,6 +402,12 @@ module sirius(
.pc_tlb_invalid_seq1 (pc_tlb_invalid_seq1),
.pc_tlb_uncached_seq1 (pc_tlb_uncached_seq1),

.pc_address_psy_next_seq2(pc_address_psy_next_seq2),
.pc_tlb_miss_seq2 (pc_tlb_miss_seq2),
.pc_tlb_illegal_seq2 (pc_tlb_illegal_seq2),
.pc_tlb_invalid_seq2 (pc_tlb_invalid_seq2),
.pc_tlb_uncached_seq2 (pc_tlb_uncached_seq2),

.pc_address (if_pc_address),
.pc_address_psy (inst_addr),
.tlb_miss (if_inst_miss),
Expand Down Expand Up @@ -959,6 +971,14 @@ module sirius(
.inst_illegal_2 (pc_tlb_illegal_seq1),
.inst_tlb_invalid_2 (pc_tlb_invalid_seq1),

.iaddr_3 (mem_exception_address),
.inst_en_3 (1'd1),
.iaddr_psy_3 (pc_address_psy_next_seq2),
.inst_uncached_3 (pc_tlb_uncached_seq2),
.inst_miss_3 (pc_tlb_miss_seq2),
.inst_illegal_3 (pc_tlb_illegal_seq2),
.inst_tlb_invalid_3 (pc_tlb_invalid_seq2),

.daddr (id_ex_daddr),
.data_en (id_ex_mem_type != `MEM_NOOP),
.daddr_psy (ex_daddr_psy),
Expand Down
22 changes: 22 additions & 0 deletions tlb_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,12 @@ module tlb_top(
output logic valid_inst_2,
output logic uncached_inst_2,

input [31:0] vaddr_inst_3,
output logic [31:0] paddr_inst_3,
output logic miss_inst_3,
output logic valid_inst_3,
output logic uncached_inst_3,

input [31:0] vaddr_data,
output logic [31:0] paddr_data,
output logic miss_data,
Expand Down Expand Up @@ -92,6 +98,22 @@ module tlb_top(
.cp0_tlb_conf_in (cp0_tlb_conf_in)
);

tlb_common tlb_inst_3(
.clk (clk),
.rst (rst),
.tlbwi (tlbwi),
.tlbwr (tlbwr),
.curr_ASID (curr_ASID),
.vaddr (vaddr_inst_3),
.paddr (paddr_inst_3),
.miss (miss_inst_3),
.valid (valid_inst_3),
.uncached (uncached_inst_3),
.cp0_index (cp0_index),
.cp0_random (cp0_random),
.cp0_tlb_conf_in (cp0_tlb_conf_in)
);

tlb_common tlb_data(
.clk (clk),
.rst (rst),
Expand Down

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