Skip to content

vizionerco/RISC-V

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

23 Commits
 
 
 
 
 
 
 
 

Repository files navigation

About Reposity

This repository includes documents, source codes and related work for my (see below owner section) attemp to design RISC-V cores and suport materials.

requirements/ folder is for requirements list of RISC-V derived from official documents

requirements/RL_Unprivileged_ISA_20191213.pdf : Requirements list of The RISC-V Instruction Set Manual Volume I: Unprivileged ISA V20191213

requirements/RL_Privileged_ISA_20211203.pdf : Requirements list of The RISC-V Instruction Set Manual Volume II: Privileged Architecture V20211203

requirements/RL_IOMMU_V1_0.pdf : Requirements list of The RISC-V IOMMU Architecture Specification version 1.0

requirements/RL_PLIC_V1_0_0.pdf : Requirements list of RISC-V Platform-Level Interrupt Controller Specification version 1.0

requirements/RL_AIA_V1_0.pdf : Requirements list of The RISC-V Advanced Interrupt Architecture version 1.0

requirements/RL_SBI_V2_0.pdf : Requirements list of RISC-V Supervisor Binary Interface Specification, document version 2.0

requirements/RL_UEFI_V1_0.pdf : Requirements list of RISC-V UEFI PROTOCOL Specification, document version 1.0

requirements/RL_ABIs_V1_0.pdf : Requirements List of RISC-V ABIs Specification, Document Version 1.0

requirements/RL_Trace_V2_03.pdf : Requirements List of Efficient Trace for RISC-V Version 2.0.3

requirements/RL_Debug_V0_13_2.pdf : Requirements List of RISC-V External Debug Support version 0.13.2

About Reposity Owner

After 34 years of my career, I retired from my regular job in 2023. Now, I do part time consulting services to interested parties, while I do work on projects that interest me more than a regular work.

In my career I dealt with very diverse fields of engineering: Academics, C/C++ desktop programming, embedded systems, analog circuit design, DSP algorithms, VLSI/FPGA design, underwater acoustics are to name few. I’ve always enjoyed designing controllers and processors with generic HDL for VLSI or FPGA. So, as my personal project to work on, I decided to design RISC-V cores with different capabilities.

Best regards, Mehmet Öner, Ph.D. www.linkedin.com/in/mehmet-oner-00453733/

About

RISC-V design and support materials by M. Öner

Topics

Resources

License

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published