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The multi-master I2C Controller (MMI2CC) is a custom IP capable of handling simultaneous I2C transactions on up to 26 I2C interfaces. The IP has one AXI4-Lite slave interface and 25 Avalon master interfaces. The AXI interface shall be connected to a processor for managing the IP and the Avalon interfaces need to be connected to I2C master IPs (Such as Intel Avalon I2C master). Presently the IP is configured to manage 12 LDC interfaces and 12 ADC interfaces. 2 interfaces are unused. Note that the final I2C transactions on the I2C bus are managed by the I2C master IP cores interfaced with MMI2CC. MMI2CC only manages read and write operations to the I2C masters. Thus the software driver should configure the I2C master IPs through MMI2CC to achieve the required I2C operation.
A simplified block diagram of the MMI2CC is shown in figure below. Through software the internal registers of the IP are configured which in turn control the avalon interfaces. Avalon interfaces 0-11 are grouped together (assuming they will be all interfaced with I2C masters for LDC). Similarly interfaces 12-23 are also grouped together (assuming they will be all interfaced with I2C masters for ADC). I2C transactions happens concurrently on a group. This means during an I2C write operation, same data will be written to every I2C masters within a group.
During read operation, all I2C master read operations are initialized concurrently and the read data is stored in multiple registers (one per I2C master) simultaneously. Later software can read from the internal registers to obtain the read data.
The register map of the IP is given below
| Register | AXI address Offset (decimal) | Function |
|---|---|---|
| slv_reg0 | 0 | group-0 address register |
| slv_reg1 | 4 | group-0 write data register |
| slv_reg2 | 8 | group-0 control register |
| slv_reg3 to slv_reg14 | 12 to 56 | group-0 read data registers |
| slv_reg16 | 64 | group-1 address register |
| slv_reg17 | 68 | group-1 write data register |
| slv_reg18 | 72 | group-1 control register |
| slv_reg19 to slv_reg30 | 76 to 120 | group-1 read data registers |
To initialize a write transaction to the I2C master IPs, the software first writes the avalon register address of the I2C master to the MMI2CC IP (slv_reg0 for group-0 and slav_reg16 for group-1). It then writes the data to write data registers (slv_reg1 for group-0 and slav_reg17 for group-1). Then it writes 0x1 to the control register (slv_reg2 for group-0 and slav_reg18 for group-1). As soon as the control register is configured, MMI2CC initalizes an avalon write operation and writes the same data to same register of every I2C master.
To initialize a read transaction to the I2C master IPs, the software first writes the avalon register address of the I2C master to the MMI2CC IP (slv_reg0 for group-0 and slav_reg16 for group-1). It writes 0x0 to the control register (slv_reg2 for group-0 and slav_reg18 for group-1). As soon as the control register is configured, MMI2CC initalizes an avalon read operation and concurrently latches the data read from the I2C masters in its internal registers (slv_reg3 to slv_reg14 for group-0 and slv_reg19 to slv_reg30 for group-1). The software driver can later read these slave registers.
The hardware device is abstracted in the user space driver of MMI2CC as a structure
typedef struct multi_i2c_master{
int BaseAddress;
void* virtualAddress;
}multi_i2c_master;
The user should create a structure variable and use the init_multi_i2c_master() function to initialize it. The BaseAddress of the IP should be obtained from the system design software (such as Quartus Platform Designer).
| API | Parameters | Function |
|---|---|---|
init_multi_i2c_master() |
multi_i2c_master* instancePntr int BaseAddress
|
Initializes the MMCI2CC structure. User should provide a pointer to the MMCI2CC structure and the BaseAddress obtained from system design software |
writeRegI2C() |
multi_i2c_master* instancePntrint Groupint RegAddress int Data
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readRegI2C() |
multi_i2c_master* instancePntrint Groupint RegAddress
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readI2CData() |
multi_i2c_master* instancePntrint Groupint masterNumber
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| Following APIs can be used only if the I2C master interfaced with MMI2CC is Intel's Avalon I2C master controller | ||
enableI2C() |
multi_i2c_master* instancePntrint Group
|
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disableI2C() |
multi_i2c_master* instancePntrint Group
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setI2CSpeed() |
multi_i2c_master* instancePntrint Group,int I2C_Speed
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EnableInterrupt() |
multi_i2c_master* instancePntrint Group, int intrMask
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clearInterrupt() |
multi_i2c_master* instancePntrint Group int intrMask
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