Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.
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Updated
Feb 14, 2017 - Verilog
Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.
IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator
Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation
Synthesizable SystemVerilog IP-Core of the I2S Receiver
Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)
A Python-based IP Core Management Infrastructure.
Artículos escritos en base al Proyecto Final de la carrera Ingeniería en Computación FCEFyN UNC
Informe de la Tesis para la Carrera en Ingeniería en Computación FCEFyN UNC
Código Verilog y C realizado para la tesis para la Carrera en Ingeniería en Computación FCEFyN UNC
Microarquitecturas y Softcores - CESE - FIUBA
FPGA-based high performance MPEG2 encoder for video compression. 基于FPGA的高性能MPEG2视频编码器,可实现视频压缩。
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