VeeR EH1 core
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Updated
May 29, 2023 - SystemVerilog
VeeR EH1 core
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
QKeras: a quantization deep learning library for Tensorflow Keras
VeeR EL2 Core
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
Convolutional accelerator kernel, target ASIC & FPGA
Open Application-Specific Instruction Set processor tools (OpenASIP)
IC implementation of Systolic Array for TPU
Standard Cell Library based Memory Compiler using FF/Latch cells
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
hardware design of universal NPU(CNN accelerator) for various convolution neural network
I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be …
A place to keep my synthesizable verilog examples.
Quasar 2.0: Chisel equivalent of SweRV-EL2
KiCad symbol library for sky130 and gf180mcu PDKs
RISCV CPU implementation in SystemVerilog
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
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