#

ip-core

Here are 24 public repositories matching this topic...

gonzafernan / cese-mys-zynq7

Microarquitecturas y Softcores - CESE - FIUBA

verilog verilog-hdl xilinx-vivado ip-core xilinx-zynq

Updated Dec 13, 2023
Verilog

rubinsteina13 / SV_CLARKE_TRANSFORMATION_CORES

Synthesizable SystemVerilog IP-Cores of the Forward and Backward Clarke Transformation

fpga verilog systemverilog digital-signal-processing digital-design cpld ip-core asic-design

Updated Jun 7, 2020
SystemVerilog

esynr3z / pip-hdl

📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip

python vhdl verification vip pip verilog systemverilog ip-core rtl-design

Updated Jan 26, 2024
Python

sbaldzenka / uart_core

UART IP-core for FPGA.

fpga vhdl diamond uart hdl modelsim questasim ip-core lattice-fpga machxo3

Updated Sep 19, 2022
VHDL

vedranMv / axi_spi_master

IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)

spi vhdl-modules axi axi-spi ip-core

Updated Jul 12, 2017
VHDL

magictaler / RGB-LED-PWM-Demo-for-Arty-Z7-20

RGB PWM LED Demo project running on ARTY Z7-20 hardware

freertos xilinx ip-core zynq-7020

Updated May 16, 2020
C

gvd1248 / FPGA

This repository showcases various projects developed on the DE10-Lite board (Intel MAX 10 FPGA) using Quartus Prime Lite software. The projects primarily focus on Finite State Machines (FSMs) and communication protocols, implemented in VHDL. Each project includes HDL code, testbenches, simulations, and .qsf files for pin assignments

fsm dsp vhdl verification finite-state-machine gtkwave testbench verilog-hdl digital-circuits ip-core uart-vhdl rtl-simulations

Updated Sep 5, 2024
Verilog

FlorianFrank / Verilog-UART-Custom-IP

A custom UART IP core. Wrting to bare metal I/O pins independent of the FPGA model.

fpga serial verilog xilinx vivado uart ip-core

Updated Apr 5, 2023
Verilog

jnonino-crpisetta-icomp / implementacion

Código Verilog y C realizado para la tesis para la Carrera en Ingeniería en Computación FCEFyN UNC

c fpga vhdl concurrent-programming computer-engineering verilog research-project petri-nets academic-project parallel-programming ip-core time-petri-nets timed-petri-nets

Updated Mar 6, 2023
C

jnonino-crpisetta-icomp / articulos

Artículos escritos en base al Proyecto Final de la carrera Ingeniería en Computación FCEFyN UNC

fpga vhdl concurrent-programming computer-engineering verilog academic-publication petri-nets papers parallel-programming ip-core time-petri-nets timed-petri-nets

Updated Mar 6, 2023
TeX

rubinsteina13 / SV_DSM_CORE

Synthesizable SystemVerilog IP-Core of the First-Order Delta-Sigma Modulator

fpga verilog digital-signal-processing system-verilog cpld dac ip-core asic-design

Updated Jun 6, 2020
SystemVerilog

iDoka / ipyxact

Python-based IP-XACT parser

asic fpga xml eda spirit rtl asciidoc ip verilog ip-xact soc vlsi uvm ip-core design-automation accellera ieee-1685 ieee1685

Updated Mar 27, 2017
Python

jnonino-crpisetta-icomp / informe

Informe de la Tesis para la Carrera en Ingeniería en Computación FCEFyN UNC

c latex fpga thesis vhdl latex-document concurrent-programming computer-engineering verilog report petri-nets parallel-programming ip-core time-petri-nets timed-petri-nets

Updated Mar 6, 2023
TeX

Goshik92 / FpgaCha

Implementation of ChaCha20 for Cyclone V FPGA (DE10-nano) easily connectable to HPS (ARM processor)

arm cryptography encryption fpga verilog altera systemverilog hdl soc chacha20 dma cyclone-v ip-core hps rfc7539 platform-designer rfc8439

Updated Jul 29, 2020
C++

iDoka / GOST-R34.12-2015

Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.

asic crypto fpga cipher rtl verilog xilinx altera grasshopper hdl kuznyechik ip-core gost-r34-12-2015 rfc7801 s-box

Updated Feb 14, 2017
Verilog

iDoka / ipxact-cli-tools

IP-XACT based CLI-tools

asic fpga xml eda spirit rtl asciidoc ip verilog ip-xact soc vlsi uvm ip-core design-automation accellera ieee-1685 ieee1685

Updated Apr 12, 2017
Mako

rubinsteina13 / SV_I2S_RX_CORE

Synthesizable SystemVerilog IP-Core of the I2S Receiver

fpga verilog systemverilog hdl system-verilog cpld i2s i2s-dac ip-core asic-design

Updated Jun 7, 2020
SystemVerilog

iDoka / GOST-28147-89

Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher

asic crypto fpga cipher rtl verilog xilinx altera hdl magma ip-core gost-28147-89 gost-r34-11-94 rfc4357 gost-28147 rfc5831 rfc4490 s-box gost-r34-10-2012

Updated Feb 27, 2024
Verilog

alexo-git / AIC1106-IPcore

The Altera Avalon bus IP core for TI AIC1106 PCM Codec and Software Driver Example

fpga voice verilog pcm altera ip-core tlv320aic1106

Updated Feb 18, 2019
C

rohitk-singh / usb-device

USB 2.0 Device IP core using Migen with out-of-box AXI Slave Interface

usb python3 usb-devices migen ip-core

Updated Oct 24, 2017
Verilog

Improve this page

Add a description, image, and links to the ip-core topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the ip-core topic, visit your repo's landing page and select "manage topics."