RTL Verification Engineer
Dhaka, Bangladesh

I am highly enthusiastic about hardware verification and UVM Development. I possess a solid understanding of Digital Design Concepts, Hardware Description Languages such as Verilog and SystemVerilog, and Verification Methodologies. I am keen on expanding my knowledge and skills in hardware verification, UVM, and its practical implementation.

• 2020 - 2021

• 2015 - 2020

• Universal Verification Methodology (UVM)
• Functional Verification
• Functional Coverage
• System Verilog Assertion (SVA)
• Verilog
• SystemVerilog
• Shell Scripting (Bash)
• Digital Designs
• Object-Oriented Programming (OOP)
• IC Physical Design (PnR)
• Analog Circuit Design
• IC layout Design

• Developed test-cases and did APB verification using Universal Verification Methodology (UVM). Also, Implemented Functional Coverage and Validate the Behavior of the Design by Assertion Based Verification during the Verification Process.

• Developed test-cases for SISO, and PISO Universal Register IP and did Functional Verification using UVM.

• LinkedIn: Amit Sikder's LinkedIn Profile
• Email: amit.sder@gmail.com