Added requirement for 4B accesses to be atomic if 4B aligned

zilsd.adoc

@@ -35,12 +35,17 @@ The Zilsd extension adds the following RV32-only instructions:
 
 [NOTE]
 ====
-As the access size is 64-bit, accesses are only considered naturally aligned for effective addresses that are a multiple of 8. In this case, these instruction are guaranteed to not raise an address-misaligned exception.
+As the access size is 64-bit, accesses are only considered naturally aligned for effective addresses that are a multiple of 8.
+In this case, these instruction are guaranteed to not raise an address-misaligned exception.
+Even if naturally aligned, the memory access might not be performed atomically.
 ====
 
+If the effective address is a multiple of 4, then each word access is required to be performed atomically.
+The LD instruction must however write the loaded data to the pair of destination registers atomically to ensure fault handling is possible.
+
 [NOTE]
 ====
-Implementations may need to crack these instructions, and perform two memory operations in sequence. Therefore, implementations are not required to ensure atomicity when storing to memory. However, writing to both registers written by a 64-bit load must happen atomically to ensure fault handling is possible.
+If an implementation performs a doubleword access atomically, the mentioned atomicity requirements are inherently fulfilled.
 ====
 
 [[zcmlsd, Zcmlsd]]