Merge pull request #2 from vyoma-systems/upstream_new

upstream for dev

CHANGELOG.md

@@ -2,12 +2,14 @@
 
 This project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+
 Please note the header `WIP-DEV` is to always remain indicating the changes done on the dev branch.
 Only when a release to the main branch is done, the contents of the WIP-DEV are put under a
 versioned header while the `WIP-DEV` is left empty
 
 ## [0.12.2] - 2024-03-06
-- Add Zfa support.
+- Add Zfa support. (PR#60)
+- Initial covergroups for Zvk* instructions (PR#61)
 
 ## [0.12.1] - 2024-02-27
 - Fix test.yml

riscv_ctg/data/imc.yaml

@@ -1862,6 +1862,7 @@ c.jr:
   isa: 
     - IC
   formattype: 'crformat'
+  ea_align_data: '[0,1]'
   rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)'
   rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)'
   template: |-
@@ -1880,6 +1881,7 @@ c.jalr:
   isa: 
     - IC
   formattype: 'crformat'
+  ea_align_data: '[0,1]' 
   rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)'
   rs2_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)'
   template: |-

riscv_ctg/generator.py

@@ -264,7 +264,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str):
         self.is_fext = is_fext
         self.is_nan_box = is_nan_box
 
-        if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","flw","fsw","fld","fsd", "ldz","sdz"]:
+        if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd","ldz","sdz"]:
             self.val_vars = self.val_vars + ['ea_align']
         self.template = opnode['template']
         self.opnode = opnode
@@ -1433,4 +1433,4 @@ def __write_test__(self, file_name,node,label,instr_dict, op_node, usage_str):
         sign.append("#ifdef rvtest_gpr_save\n"+signode_template.substitute(
             {'n':32,'label':"gpr_save",'sz':'XLEN/32'})+"\n#endif\n")
         with open(file_name,"w") as fd:
-            fd.write(usage_str + test_template.safe_substitute(data='\n'.join(data),test=test,sig='\n'.join(sign),isa=op_node_isa,opcode=opcode,extension=extension,label=label))
+            fd.write(usage_str + test_template.safe_substitute(data='\n'.join(data),test=test,sig='\n'.join(sign),isa=op_node_isa,opcode=opcode,extension=extension,label=label))

sample_cgfs/dataset.cgf

@@ -120,6 +120,40 @@ datasets:
     f30: 0
     f31: 0
 
+  all_vregs: &all_vregs
+    v0: 0
+    v1: 0
+    v2: 0
+    v3: 0
+    v4: 0
+    v5: 0
+    v6: 0
+    v7: 0
+    v8: 0
+    v9: 0
+    v10: 0
+    v11: 0
+    v12: 0
+    v13: 0
+    v14: 0
+    v15: 0
+    v16: 0
+    v17: 0
+    v18: 0
+    v19: 0
+    v20: 0
+    v21: 0
+    v22: 0
+    v23: 0
+    v24: 0
+    v25: 0
+    v26: 0
+    v27: 0
+    v28: 0
+    v29: 0
+    v30: 0
+    v31: 0
+
   pair_regs: &pair_regs
     x2: 0
     x4: 0

sample_cgfs/rv32i_priv.cgf

@@ -85,6 +85,22 @@ misalign1-jalr:
     'imm_val%2 == 1 and ea_align == 1': 0
     'imm_val%2 == 0 and ea_align == 1': 0
 
+misalign1-cjalr:
+  config: 
+    - check ISA:=regex(.*I.*C.*); def rvtest_mtrap_routine=True
+  mnemonics:
+    c.jalr: 0
+  val_comb:
+    'ea_align == 1': 0
+
+misalign1-cjr:
+  config: 
+    - check ISA:=regex(.*I.*C.*); def rvtest_mtrap_routine=True
+  mnemonics:
+    c.jr: 0
+  val_comb:
+    'ea_align == 1': 0
+
 misalign-jal:
   config:
     - check ISA:=regex(.*I.*C.*)

sample_cgfs/rv64i_priv.cgf

@@ -126,6 +126,22 @@ misalign1-jalr:
   val_comb:
     'ea_align == 1': 0
 
+misalign1-cjalr:
+  config: 
+    - check ISA:=regex(.*I.*C.*); def rvtest_mtrap_routine=True
+  mnemonics:
+    c.jalr: 0
+  val_comb:
+    'ea_align == 1': 0
+
+misalign1-cjr:
+  config: 
+    - check ISA:=regex(.*I.*C.*); def rvtest_mtrap_routine=True
+  mnemonics:
+    c.jr: 0
+  val_comb:
+    'ea_align == 1': 0
+
 misalign-jal:
   config:
     - check ISA:=regex(.*I.*C.*)

sample_cgfs/zvk/vaesdf.cgf

@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vaesdf.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesdf.vv: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0
+
+vaesdf.vs:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesdf.vs: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0

sample_cgfs/zvk/vaesdm.cgf

@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vaesdm.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesdm.vv: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0
+
+vaesdm.vs:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesdm.vs: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0

sample_cgfs/zvk/vaesef.cgf

@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vaesef.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesef.vv: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0
+
+vaesef.vs:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesef.vs: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0

sample_cgfs/zvk/vaesem.cgf

@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vaesem.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesem.vv: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0
+
+vaesem.vs:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesem.vs: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0

sample_cgfs/zvk/vaeskf1.cgf

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vaeskf1.vi:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaeskf1.vi: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0

sample_cgfs/zvk/vaeskf2.cgf

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vaeskf2.vi:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaeskf2.vi: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0

sample_cgfs/zvk/vaesz.cgf

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vaesz.vs:
+    config:
+      - check ISA:=(.*I.*V.*Zvkned)
+    mnemonics:
+      vaesz.vs: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0
+
+

sample_cgfs/zvk/vandn.cgf

@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vandn.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vandn.vv: 0
+    rs1:
+      <<: *all_vregs
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      <<: *sfmt_op_comb
+
+vandn.vx:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vandn.vx: 0
+    rs1:
+      <<: *all_regs
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      <<: *sfmt_op_comb

sample_cgfs/zvk/vbrev8.cgf

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vbrev8.v:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vbrev8.v: 0
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      'rs2 == rd and rs2 != 0': 0
+      'rs2 != rd and rs2 != 0': 0

sample_cgfs/zvk/vclmul.cgf

@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vclmul.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vclmul.vv: 0
+    rs1:
+      <<: *all_vregs
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      <<: *sfmt_op_comb
+
+vclmul.vx:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vclmul.vx: 0
+    rs1:
+      <<: *all_regs
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      <<: *sfmt_op_comb

sample_cgfs/zvk/vclmulh.cgf

@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+vclmulh.vv:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vclmulh.vv: 0
+    rs1:
+      <<: *all_vregs
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      <<: *sfmt_op_comb
+
+vclmulh.vx:
+    config:
+      - check ISA:=(.*I.*V.*Zvkb)
+    mnemonics:
+      vclmulh.vx: 0
+    rs1:
+      <<: *all_regs
+    rs2:
+      <<: *all_vregs
+    rd:
+      <<: *all_vregs
+    op_comb:
+      <<: *sfmt_op_comb