add drivers

src/main/scala/jigsaw/SramHarness.scala

@@ -0,0 +1,65 @@
+package jigsaw
+import caravan.bus.tilelink.{TLRequest, TLResponse, TilelinkConfig, TilelinkDevice, TilelinkHost}
+import caravan.bus.wishbone.{WBRequest, WBResponse, WishboneConfig, WishboneDevice, WishboneHost}
+import chisel3._
+import chisel3.stage.ChiselStage
+import chisel3.util.Decoupled
+// import jigsaw.peripherals.spiflash.{Config,Spi}
+import jigsaw.rams.sram._
+
+class SramHarness(implicit val config: WishboneConfig ) extends Module {
+  val io = IO(new Bundle {
+
+    // bus interconnect interfaces
+    val req = Flipped(Decoupled(new WBRequest()))
+    val rsp = Decoupled(new WBResponse())
+  })
+  val hostAdapter = Module(new WishboneHost())
+  val deviceAdapter = Module(new WishboneDevice())
+  val sram = Module(new SRAM1kb(new WBRequest(), new WBResponse()))
+
+  hostAdapter.io.reqIn <> io.req
+  io.rsp <> hostAdapter.io.rspOut
+  hostAdapter.io.wbMasterTransmitter <> deviceAdapter.io.wbMasterReceiver
+  hostAdapter.io.wbSlaveReceiver <> deviceAdapter.io.wbSlaveTransmitter
+
+  sram.io.req <> deviceAdapter.io.reqOut
+  sram.io.rsp <> deviceAdapter.io.rspIn
+}
+
+object SramDriverWB extends App {
+  implicit val config = WishboneConfig(32,32)
+//   implicit val spiConfig = Config()
+  (new ChiselStage).emitVerilog(new SramHarness())
+}
+
+
+
+
+class SramHarnessTL(implicit val config: TilelinkConfig ) extends Module {
+  val io = IO(new Bundle {
+
+    // bus interconnect interfaces
+    val req = Flipped(Decoupled(new TLRequest()))
+    val rsp = Decoupled(new TLResponse())
+
+  })
+  val hostAdapter = Module(new TilelinkHost())
+  val deviceAdapter = Module(new TilelinkDevice())
+  val sram = Module(new SRAM1kb(new TLRequest(), new TLResponse()))
+
+  hostAdapter.io.reqIn <> io.req
+  io.rsp <> hostAdapter.io.rspOut
+  hostAdapter.io.tlMasterTransmitter <> deviceAdapter.io.tlMasterReceiver
+  hostAdapter.io.tlSlaveReceiver <> deviceAdapter.io.tlSlaveTransmitter
+
+  sram.io.req <> deviceAdapter.io.reqOut
+  sram.io.rsp <> deviceAdapter.io.rspIn
+
+}
+
+object SramDriverTL extends App {
+  implicit val config = TilelinkConfig()
+//   implicit val spiConfig = Config()
+  (new ChiselStage).emitVerilog(new SramHarnessTL())
+}

src/main/scala/jigsaw/TimerHarness.scala

@@ -0,0 +1,78 @@
+package jigsaw
+import caravan.bus.tilelink.{TLRequest, TLResponse, TilelinkConfig, TilelinkDevice, TilelinkHost}
+import caravan.bus.wishbone.{WBRequest, WBResponse, WishboneConfig, WishboneDevice, WishboneHost}
+import chisel3._
+import chisel3.stage.ChiselStage
+import chisel3.util.Decoupled
+// import jigsaw.peripherals.spiflash.{Config,Spi}
+// import jigsaw.rams.sram._
+import jigsaw.peripherals.timer._
+
+class TimerHarness(implicit val config: WishboneConfig ) extends Module {
+  val io = IO(new Bundle {
+
+    // bus interconnect interfaces
+    val req = Flipped(Decoupled(new WBRequest()))
+    val rsp = Decoupled(new WBResponse())
+
+    val cio_timer_intr_cmp = Output(Bool())
+    val cio_timer_intr_ovf = Output(Bool())
+  })
+  val hostAdapter = Module(new WishboneHost())
+  val deviceAdapter = Module(new WishboneDevice())
+  val timer = Module(new Timer(new WBRequest(), new WBResponse()))
+
+  hostAdapter.io.reqIn <> io.req
+  io.rsp <> hostAdapter.io.rspOut
+  hostAdapter.io.wbMasterTransmitter <> deviceAdapter.io.wbMasterReceiver
+  hostAdapter.io.wbSlaveReceiver <> deviceAdapter.io.wbSlaveTransmitter
+
+  timer.io.req <> deviceAdapter.io.reqOut
+  timer.io.rsp <> deviceAdapter.io.rspIn
+
+  io.cio_timer_intr_cmp := timer.io.cio_timer_intr_cmp
+  io.cio_timer_intr_ovf := timer.io.cio_timer_intr_ovf
+}
+
+object TimerDriverWB extends App {
+  implicit val config = WishboneConfig(32,32)
+//   implicit val spiConfig = Config()
+  (new ChiselStage).emitVerilog(new TimerHarness())
+}
+
+
+
+
+class TimerHarnessTL(implicit val config: TilelinkConfig ) extends Module {
+  val io = IO(new Bundle {
+
+    // bus interconnect interfaces
+    val req = Flipped(Decoupled(new TLRequest()))
+    val rsp = Decoupled(new TLResponse())
+
+    val cio_timer_intr_cmp = Output(Bool())
+    val cio_timer_intr_ovf = Output(Bool())
+
+  })
+  val hostAdapter = Module(new TilelinkHost())
+  val deviceAdapter = Module(new TilelinkDevice())
+  val timer = Module(new Timer(new TLRequest(), new TLResponse()))
+
+  hostAdapter.io.reqIn <> io.req
+  io.rsp <> hostAdapter.io.rspOut
+  hostAdapter.io.tlMasterTransmitter <> deviceAdapter.io.tlMasterReceiver
+  hostAdapter.io.tlSlaveReceiver <> deviceAdapter.io.tlSlaveTransmitter
+
+  timer.io.req <> deviceAdapter.io.reqOut
+  timer.io.rsp <> deviceAdapter.io.rspIn
+
+  io.cio_timer_intr_cmp := timer.io.cio_timer_intr_cmp
+  io.cio_timer_intr_ovf := timer.io.cio_timer_intr_ovf
+
+}
+
+object TimerDriverTL extends App {
+  implicit val config = TilelinkConfig()
+//   implicit val spiConfig = Config()
+  (new ChiselStage).emitVerilog(new TimerHarnessTL())
+}

src/main/scala/jigsaw/gpioHarness.scala

@@ -0,0 +1,88 @@
+package jigsaw
+
+import caravan.bus.tilelink.{TLRequest, TLResponse, TilelinkConfig, TilelinkDevice, TilelinkHost}
+import caravan.bus.wishbone.{WBRequest, WBResponse, WishboneConfig, WishboneDevice, WishboneHost}
+import chisel3._
+import chisel3.stage.ChiselStage
+import chisel3.util.Decoupled
+import jigsaw.peripherals.gpio._
+
+class gpioHarness(implicit val config: WishboneConfig) extends Module {
+  val io = IO(new Bundle {
+
+    // bus interconnect interfaces
+    val req = Flipped(Decoupled(new WBRequest()))
+    val rsp = Decoupled(new WBResponse())
+
+    // UART interfaces
+
+    val cio_gpio_i = Input(UInt(32.W))
+    val cio_gpio_o = Output(UInt(32.W))
+    val cio_gpio_en_o = Output(UInt(32.W))
+    val intr_gpio_o = Output(UInt(32.W))
+
+  })
+  val hostAdapter = Module(new WishboneHost())
+  val deviceAdapter = Module(new WishboneDevice())
+  val gpio_wrapper = Module(new Gpio(new WBRequest(), new WBResponse()))
+
+  hostAdapter.io.reqIn <> io.req
+  io.rsp <> hostAdapter.io.rspOut
+  hostAdapter.io.wbMasterTransmitter <> deviceAdapter.io.wbMasterReceiver
+  hostAdapter.io.wbSlaveReceiver <> deviceAdapter.io.wbSlaveTransmitter
+
+  gpio_wrapper.io.req <> deviceAdapter.io.reqOut
+  gpio_wrapper.io.rsp <> deviceAdapter.io.rspIn
+
+    gpio_wrapper.io.cio_gpio_i := io.cio_gpio_i
+    io.cio_gpio_o := gpio_wrapper.io.cio_gpio_o
+    io.cio_gpio_en_o := gpio_wrapper.io.cio_gpio_en_o
+    io.intr_gpio_o := gpio_wrapper.io.intr_gpio_o
+}
+
+object GPIOHarnessDriver extends App {
+  implicit val config = WishboneConfig(32,32)
+  (new ChiselStage).emitVerilog(new gpioHarness())
+}
+
+
+
+
+class gpioHarness_TL(implicit val config: TilelinkConfig) extends Module {
+  val io = IO(new Bundle {
+
+    // bus interconnect interfaces
+    val req = Flipped(Decoupled(new TLRequest()))
+    val rsp = Decoupled(new TLResponse())
+
+    // UART interfaces
+
+    val cio_gpio_i = Input(UInt(32.W))
+    val cio_gpio_o = Output(UInt(32.W))
+    val cio_gpio_en_o = Output(UInt(32.W))
+    val intr_gpio_o = Output(UInt(32.W))
+
+
+  })
+  val hostAdapter = Module(new TilelinkHost())
+  val deviceAdapter = Module(new TilelinkDevice())
+  val gpio_wrapper = Module(new Gpio(new TLRequest(), new TLResponse()))
+
+  hostAdapter.io.reqIn <> io.req
+  io.rsp <> hostAdapter.io.rspOut
+  hostAdapter.io.tlMasterTransmitter <> deviceAdapter.io.tlMasterReceiver
+  hostAdapter.io.tlSlaveReceiver <> deviceAdapter.io.tlSlaveTransmitter
+
+  gpio_wrapper.io.req <> deviceAdapter.io.reqOut
+  gpio_wrapper.io.rsp <> deviceAdapter.io.rspIn
+
+    gpio_wrapper.io.cio_gpio_i := io.cio_gpio_i
+    io.cio_gpio_o := gpio_wrapper.io.cio_gpio_o
+    io.cio_gpio_en_o := gpio_wrapper.io.cio_gpio_en_o
+    io.intr_gpio_o := gpio_wrapper.io.intr_gpio_o
+}
+
+object GPIOHarnessDriverTL extends App {
+  implicit val config = TilelinkConfig()
+  (new ChiselStage).emitVerilog(new gpioHarness_TL())
+}

src/main/scala/jigsaw/i2cHarness.scala

@@ -0,0 +1,86 @@
+package jigsaw
+
+import caravan.bus.tilelink.{TLRequest, TLResponse, TilelinkConfig, TilelinkDevice, TilelinkHost}
+import caravan.bus.wishbone.{WBRequest, WBResponse, WishboneConfig, WishboneDevice, WishboneHost}
+import chisel3._
+import chisel3.stage.ChiselStage
+import chisel3.util.Decoupled
+import jigsaw.peripherals.i2c._
+
+class i2cHarness(implicit val config: WishboneConfig) extends Module {
+  val io = IO(new Bundle {
+
+    // bus interconnect interfaces
+    val req = Flipped(Decoupled(new WBRequest()))
+    val rsp = Decoupled(new WBResponse())
+
+    // I2C interfaces
+
+    val i2c_sda = Output(Bool())
+    val i2c_scl = Output(Bool())
+    val i2c_intr = Output(Bool())
+    // val i2c_sda_in = Input(Bool())
+
+  })
+  val hostAdapter = Module(new WishboneHost())
+  val deviceAdapter = Module(new WishboneDevice())
+  val i2c_wrapper = Module(new i2c(new WBRequest(), new WBResponse()))
+
+  hostAdapter.io.reqIn <> io.req
+  io.rsp <> hostAdapter.io.rspOut
+  hostAdapter.io.wbMasterTransmitter <> deviceAdapter.io.wbMasterReceiver
+  hostAdapter.io.wbSlaveReceiver <> deviceAdapter.io.wbSlaveTransmitter
+
+  i2c_wrapper.io.request <> deviceAdapter.io.reqOut
+  i2c_wrapper.io.response <> deviceAdapter.io.rspIn
+
+    // i2c_wrapper.io.cio_uart_rx_i := io.cio_uart_rx_i
+    io.i2c_sda := i2c_wrapper.io.cio_i2c_sda
+    io.i2c_scl := i2c_wrapper.io.cio_i2c_scl
+    io.i2c_intr := i2c_wrapper.io.cio_i2c_intr
+}
+
+object I2CHarnessDriver extends App {
+  implicit val config = WishboneConfig(32,32)
+  (new ChiselStage).emitVerilog(new i2cHarness())
+}
+
+
+
+
+class i2cHarness_TL(implicit val config: TilelinkConfig) extends Module {
+  val io = IO(new Bundle {
+
+    // bus interconnect interfaces
+    val req = Flipped(Decoupled(new TLRequest()))
+    val rsp = Decoupled(new TLResponse())
+
+    // I2C interfaces
+
+    val i2c_sda = Output(Bool())
+    val i2c_scl = Output(Bool())
+    val i2c_intr = Output(Bool())
+
+  })
+  val hostAdapter = Module(new TilelinkHost())
+  val deviceAdapter = Module(new TilelinkDevice())
+  val i2c_wrapper = Module(new i2c(new TLRequest(), new TLResponse()))
+
+  hostAdapter.io.reqIn <> io.req
+  io.rsp <> hostAdapter.io.rspOut
+  hostAdapter.io.tlMasterTransmitter <> deviceAdapter.io.tlMasterReceiver
+  hostAdapter.io.tlSlaveReceiver <> deviceAdapter.io.tlSlaveTransmitter
+
+  i2c_wrapper.io.request <> deviceAdapter.io.reqOut
+  i2c_wrapper.io.response <> deviceAdapter.io.rspIn
+
+    // i2c_wrapper.io.cio_uart_rx_i := io.cio_uart_rx_i
+    io.i2c_sda := i2c_wrapper.io.cio_i2c_sda
+    io.i2c_scl := i2c_wrapper.io.cio_i2c_scl
+    io.i2c_intr := i2c_wrapper.io.cio_i2c_intr
+}
+
+object I2CHarnessDriverTL extends App {
+  implicit val config = TilelinkConfig()
+  (new ChiselStage).emitVerilog(new i2cHarness_TL())
+}