Use directory of makefile instead of PWD

jxwleong · Sep 6, 2023 · 68494c1 · 68494c1
1 parent 94341bf
commit 68494c1
Showing 1 changed file with 9 additions and 8 deletions.
diff --git a/makefile b/makefile
@@ -1,18 +1,19 @@
 # Makefile
+THIS_DIR := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
 
 # defaults
 SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 
-VERILOG_SOURCES	+= $(PWD)/CombinedCUnDP.v
-VERILOG_SOURCES += $(PWD)/CU.v
-VERILOG_SOURCES += $(PWD)/DP.v
+VERILOG_SOURCES	+= $(THIS_DIR)/CombinedCUnDP.v
+VERILOG_SOURCES += $(THIS_DIR)/CU.v
+VERILOG_SOURCES += $(THIS_DIR)/DP.v
 
-VERILOG_SOURCES += $(PWD)/DFF_reg.v
-VERILOG_SOURCES += $(PWD)/RAM.v
-VERILOG_SOURCES += $(PWD)/addSubstractor.v
-VERILOG_SOURCES += $(PWD)/mux2to1.v
-VERILOG_SOURCES += $(PWD)/mux4to1.v
+VERILOG_SOURCES += $(THIS_DIR)/DFF_reg.v
+VERILOG_SOURCES += $(THIS_DIR)/RAM.v
+VERILOG_SOURCES += $(THIS_DIR)/addSubstractor.v
+VERILOG_SOURCES += $(THIS_DIR)/mux2to1.v
+VERILOG_SOURCES += $(THIS_DIR)/mux4to1.v
 # use VHDL_SOURCES for VHDL files
 
 # TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file