Update sdram clock phase and timing constraints

jefflieu · Dec 30, 2018 · f1c69af · f1c69af
1 parent 8b7c35b
commit f1c69af
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Showing 2 changed files with 6 additions and 5 deletions.
diff --git a/hw/recon_2/max1000/alt_ip/alt_pll.v b/hw/recon_2/max1000/alt_ip/alt_pll.v
@@ -114,7 +114,7 @@ module alt_pll (
 		altpll_component.clk1_divide_by = 6,
 		altpll_component.clk1_duty_cycle = 50,
 		altpll_component.clk1_multiply_by = 25,
-		altpll_component.clk1_phase_shift = "15278",
+		altpll_component.clk1_phase_shift = "0",
 		altpll_component.compensate_clock = "CLK0",
 		altpll_component.inclk0_input_frequency = 83333,
 		altpll_component.intended_device_family = "MAX 10",
@@ -230,7 +230,7 @@ endmodule
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "275.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
@@ -278,7 +278,7 @@ endmodule
 // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "6"
 // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "15278"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"

diff --git a/hw/recon_2/max1000/constraints/recon_2.sdc b/hw/recon_2/max1000/constraints/recon_2.sdc
@@ -70,15 +70,16 @@ create_generated_clock -name flash_se_clk -source pll|altpll_component|auto_gene
 #**************************************************************
 # Set Input Delay
 #**************************************************************
-set_multicycle_path -from [get_clocks {sdram_clk}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -setup -end 2
-set_input_delay -clock {sdram_clk} 4.5 [get_ports {sdram_0_dq[0] sdram_0_dq[1] sdram_0_dq[2] sdram_0_dq[3] sdram_0_dq[4] sdram_0_dq[5] sdram_0_dq[6] sdram_0_dq[7] sdram_0_dq[8] sdram_0_dq[9] sdram_0_dq[10] sdram_0_dq[11] sdram_0_dq[12] sdram_0_dq[13] sdram_0_dq[14] sdram_0_dq[15]}]
+#From the datasheet, tac = 6ns
+set_input_delay -clock {sdram_clk} 6 [get_ports {sdram_0_dq[0] sdram_0_dq[1] sdram_0_dq[2] sdram_0_dq[3] sdram_0_dq[4] sdram_0_dq[5] sdram_0_dq[6] sdram_0_dq[7] sdram_0_dq[8] sdram_0_dq[9] sdram_0_dq[10] sdram_0_dq[11] sdram_0_dq[12] sdram_0_dq[13] sdram_0_dq[14] sdram_0_dq[15]}]
 
 set_input_delay -clock { altera_reserved_tck } 10 [get_ports {altera_reserved_tdi}]
 set_input_delay -clock { altera_reserved_tck } 10 [get_ports {altera_reserved_tms}]
 
 #**************************************************************
 # Set Output Delay
 #**************************************************************
+#From the datasheet, tds = 1.5ns
 set_output_delay -clock {sdram_clk} 1.5 [get_ports {sdram_0_addr[0] sdram_0_addr[1] sdram_0_addr[2] sdram_0_addr[3] sdram_0_addr[4] sdram_0_addr[5] sdram_0_addr[6] sdram_0_addr[7] sdram_0_addr[8] sdram_0_addr[9] sdram_0_addr[10] sdram_0_addr[11] sdram_0_ba[0] sdram_0_ba[1] sdram_0_cas_n sdram_0_cke sdram_0_cs_n sdram_0_dq[0] sdram_0_dq[1] sdram_0_dq[2] sdram_0_dq[3] sdram_0_dq[4] sdram_0_dq[5] sdram_0_dq[6] sdram_0_dq[7] sdram_0_dq[8] sdram_0_dq[9] sdram_0_dq[10] sdram_0_dq[11] sdram_0_dq[12] sdram_0_dq[13] sdram_0_dq[14] sdram_0_dq[15] sdram_0_dqm[0] sdram_0_dqm[1] sdram_0_ras_n sdram_0_we_n}]
 
 set_output_delay -clock { altera_reserved_tck } 10 [get_ports {altera_reserved_tdo}]