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library IEEE; | ||
use IEEE.std_logic_1164.all; | ||
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library libCommon; | ||
use libCommon.P1.all; | ||
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entity A1 is | ||
port ( | ||
signal Clock : in std_logic | ||
); | ||
end entity; | ||
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architecture rtl of A1 is | ||
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begin | ||
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end architecture; |
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library IEEE; | ||
use IEEE.std_logic_1164.all; | ||
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library libCommon; | ||
use libCommon.P2.all; | ||
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entity A2 is | ||
port ( | ||
signal Clock : in std_logic | ||
); | ||
end entity; | ||
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architecture rtl of A2 is | ||
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begin | ||
a : entity work.A1 | ||
port map ( | ||
Clock => Clock | ||
); | ||
end architecture; |
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library libraryCommon; | ||
use libraryCommon.P2.all; | ||
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entity B1 is | ||
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end entity; | ||
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architecture rtl of B1 is | ||
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begin | ||
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end architecture; | ||
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package P1 is | ||
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end package; | ||
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package body P1 is | ||
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end package body; |
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use work.P1.all; | ||
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package P2 is | ||
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end package; | ||
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package body P2 is | ||
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end package body; |
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