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Verilog: introduce the Verilog indexer
This adds a recusive decent parser for quicky indexing large quantities of Verilog, tolerating parsing errors, for the purpose of creating overview data very quickly. A new executable, vlindex, is added to output it.
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CORE | ||
nested_case1.v | ||
--bound 0 | ||
^EXIT=0$ | ||
^SIGNAL=0$ | ||
^\[main.property.p1\] .* PROVED up to bound 0$ | ||
-- | ||
^warning: ignoring |
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module main(input x, input y); | ||
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reg result; | ||
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always @(x, y) | ||
case(x) | ||
0: result = 0; | ||
1: | ||
case(y) | ||
1: result = 1; | ||
0: result = 0; | ||
endcase | ||
endcase | ||
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always assert p1: result == (x && y); | ||
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endmodule |
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SRC = \ | ||
verilog_indexer.cpp \ | ||
vlindex_main.cpp \ | ||
vlindex_parse_options.cpp \ | ||
#empty line | ||
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OBJ+= $(CPROVER_DIR)/util/util$(LIBEXT) \ | ||
$(CPROVER_DIR)/langapi/langapi$(LIBEXT) \ | ||
$(CPROVER_DIR)/big-int/big-int$(LIBEXT) \ | ||
../verilog/verilog$(LIBEXT) | ||
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include ../config.inc | ||
include ../common | ||
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CLEANFILES = vlindex$(EXEEXT) | ||
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all: vlindex$(EXEEXT) | ||
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ifdef DEBUG | ||
CXXFLAGS += -DDEBUG | ||
endif | ||
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############################################################################### | ||
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vlindex$(EXEEXT): $(OBJ) | ||
$(LINKBIN) |
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