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prelim tests with W=32
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schnommus committed Oct 27, 2023
1 parent b81a405 commit 896142e
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Showing 4 changed files with 52 additions and 27 deletions.
10 changes: 6 additions & 4 deletions gateware/cal/cal.py
Original file line number Diff line number Diff line change
Expand Up @@ -80,10 +80,12 @@ def decode_raw_samples(n, raw, array_avg):
ch_tc_values = np.zeros(n)
while ix != n:
channel = ix
msb = raw[ix*2]
lsb = raw[ix*2+1]
value = (msb << 8) | lsb
value_tc = twos_comp(value, 16)
byte0 = raw[ix*4]
byte1 = raw[ix*4+1]
byte2 = raw[ix*4+2]
byte3 = raw[ix*4+3]
value = (byte0 << 24) | (byte1 << 16) | (byte2 << 8) | byte3
value_tc = twos_comp(value, 32)
alpha = 0.3
array_avg[channel] = alpha*value_tc + (1-alpha)*array_avg[channel]
print(channel, hex(value), value_tc, int(array_avg[channel]))
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60 changes: 40 additions & 20 deletions gateware/cal/debug_uart.sv
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,7 @@

module debug_uart #(
parameter W = 16, // sample width
parameter WM = 32, // maximum sample width
parameter DIV = 12 // baud rate == CLK / DIV
)(
input clk,
Expand All @@ -32,6 +33,16 @@ logic [7:0] dout;
logic tx1_ack;
logic [7:0] state;

logic signed [WM-1:0] adc0_ex;
logic signed [WM-1:0] adc1_ex;
logic signed [WM-1:0] adc2_ex;
logic signed [WM-1:0] adc3_ex;

assign adc0_ex = adc0;
assign adc1_ex = adc1;
assign adc2_ex = adc2;
assign adc3_ex = adc3;

uart_tx utx (
.tx(tx_o),
.data(dout),
Expand All @@ -50,26 +61,35 @@ always_ff @(posedge clk) begin
end else if(tx1_ack) begin
tx1_valid <= 1'b1;
case (state)
0: dout <= MAGIC1;
1: dout <= MAGIC2;
2: dout <= eeprom_mfg;
3: dout <= eeprom_dev;
4: dout <= eeprom_serial[31 :32-1*8];
5: dout <= eeprom_serial[32-1*8-1:32-2*8];
6: dout <= eeprom_serial[32-2*8-1:32-3*8];
7: dout <= eeprom_serial[32-3*8-1: 0];
8: dout <= jack;
// Note: we're currently only sending 2 bytes per
// sample for calibration purposes. This should
// eventually be derived from the sample width.
9: dout <= 8'((adc0 & 16'hFF00) >> 8);
10: dout <= 8'((adc0 & 16'h00FF));
11: dout <= 8'((adc1 & 16'hFF00) >> 8);
12: dout <= 8'((adc1 & 16'h00FF));
13: dout <= 8'((adc2 & 16'hFF00) >> 8);
14: dout <= 8'((adc2 & 16'h00FF));
15: dout <= 8'((adc3 & 16'hFF00) >> 8);
16: dout <= 8'((adc3 & 16'h00FF));
0: dout <= MAGIC1;
1: dout <= MAGIC2;
2: dout <= eeprom_mfg;
3: dout <= eeprom_dev;
4: dout <= eeprom_serial[32 -1:32-1*8];
5: dout <= eeprom_serial[32-1*8-1:32-2*8];
6: dout <= eeprom_serial[32-2*8-1:32-3*8];
7: dout <= eeprom_serial[32-3*8-1: 0];
8: dout <= jack;
// Channel 0
9: dout <= adc0_ex[WM -1:WM-1*8];
10: dout <= adc0_ex[WM-1*8-1:WM-2*8];
11: dout <= adc0_ex[WM-2*8-1:WM-3*8];
12: dout <= adc0_ex[WM-3*8-1: 0];
// Channel 1
13: dout <= adc1_ex[WM -1:WM-1*8];
14: dout <= adc1_ex[WM-1*8-1:WM-2*8];
15: dout <= adc1_ex[WM-2*8-1:WM-3*8];
16: dout <= adc1_ex[WM-3*8-1: 0];
// Channel 2
17: dout <= adc2_ex[WM -1:WM-1*8];
18: dout <= adc2_ex[WM-1*8-1:WM-2*8];
19: dout <= adc2_ex[WM-2*8-1:WM-3*8];
20: dout <= adc2_ex[WM-3*8-1: 0];
// Channel 3
21: dout <= adc3_ex[WM -1:WM-1*8];
22: dout <= adc3_ex[WM-1*8-1:WM-2*8];
23: dout <= adc3_ex[WM-2*8-1:WM-3*8];
24: dout <= adc3_ex[WM-3*8-1: 0];
default: begin
// Should never get here
end
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6 changes: 4 additions & 2 deletions gateware/eurorack_pmod.sv
Original file line number Diff line number Diff line change
Expand Up @@ -75,7 +75,7 @@ logic signed [W-1:0] sample_dac3;
cal #(
.W(W),
.CAL_MEM_FILE(CAL_MEM_FILE)
)cal_instance (
) cal_instance (
.clk_256fs (clk_256fs),
.clk_fs (clk_fs),
// Calibrated inputs are zeroed if jack is unplugged.
Expand All @@ -101,7 +101,9 @@ cal #(
);

// CODEC ser-/deserialiser. Sample rate derived from these clocks.
ak4619 ak4619_instance (
ak4619 #(
.W(W),
) ak4619_instance (
.rst (rst),
.clk_256fs (clk_256fs),
.clk_fs (clk_fs),
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3 changes: 2 additions & 1 deletion gateware/top.sv
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
//`define OUTPUT_CALIBRATION

module top #(
parameter int W = 16 // sample width, bits
parameter int W = 32 // sample width, bits
)(
`ifndef INTERNAL_CLOCK
input CLK,
Expand Down Expand Up @@ -175,6 +175,7 @@ eurorack_pmod #(
// Helper module to serialize some interesting state to a UART
// for bringup and calibration purposes.
debug_uart #(
.W(W),
.DIV(12) // WARN: baud rate is determined by clk_256fs / 12 !!
) debug_uart_instance (
.clk (clk_256fs),
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