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1. MIPS-5-stage-pipelined-control-and-datapath MIPS-5-stage-pipelined-control-and-datapath Public

   Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instr…

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2. akankshac-073 akankshac-073 Public

   Config files for my GitHub profile.

3. Preemptive-Test-Scheduling-in-Photonic-NoCs Preemptive-Test-Scheduling-in-Photonic-NoCs Public

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4. Memory-Subsystem-Simulator Memory-Subsystem-Simulator Public

   Memory Management Unit design consisting of a two-level hierarchical conventional TLB, L1 way-halting split cache, L2 cache, and main memory with pure paging as the memory management scheme, and pa…

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5. EEMCS-wip EEMCS-wip Public

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6. gem5 gem5 Public

   Forked from gem5/gem5

   The official repository for the gem5 computer-system architecture simulator.

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