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Serial Peripheral Interface using Verilog

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Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
Master.v		Master.v
Master_testbench.v		Master_testbench.v
README.md		README.md
SPI.v		SPI.v
SPI_testbench.v		SPI_testbench.v
Slave.v		Slave.v
Slave_testbench.v		Slave_testbench.v
design.png		design.png

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Serial Peripheral Interface using Verilog

verilog serial-peripheral-interface

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Verilog 100.0%