The implementation of a Feed Forward Equalizer (FFE) using only one adder and one multiplier. The specifications include an input data frequency of 1 MHz and an FFE clock frequency of 4 MHz. The output data is assumed to be a 12-bit signed value. The output is available after every 4 cycles of the FFE clock. This paper details the proposed design, provides pseudo code to represent the design, includes Verilog code to mimic the design behavior, and presents the netlist of the Verilog code.
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The implementation of a FFE using only one adder and one multiplier. Specifications include a 1 MHz input data frequency and a 4 MHz FFE clock frequency, with the output being a 12-bit signed value available every 4 FFE clock cycles. The paper details the design, provides pseudo code, Verilog code, the Verilog netlist, and suggests optimizations.
Omarmuhammadmu/FFE_digital_implementation
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The implementation of a FFE using only one adder and one multiplier. Specifications include a 1 MHz input data frequency and a 4 MHz FFE clock frequency, with the output being a 12-bit signed value available every 4 FFE clock cycles. The paper details the design, provides pseudo code, Verilog code, the Verilog netlist, and suggests optimizations.
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