fix: FIFO reset and state clear behavior

NYU-Processor-Design · Oct 23, 2023 · 6c1044f · 6c1044f
1 parent b5676fa
commit 6c1044f
Showing 1 changed file with 3 additions and 5 deletions.
diff --git a/rtl/AHBUart.sv b/rtl/AHBUart.sv
@@ -102,8 +102,8 @@ module AHBUart #(
       err   <= 0;
       avail <= 0;
     end else if (bp.ren) begin
-      err   <= rxErr || ((bp.addr == RX_STATE) && err);
-      avail <= rxDone || ((bp.addr == RX_DATA) && avail);
+      err   <= rxErr || ((bp.addr != RX_STATE) && err);
+      avail <= rxDone || ((bp.addr != RX_DATA) && avail);
     end else begin
       err   <= rxErr || err;
       avail <= rxDone || avail;
@@ -214,9 +214,7 @@ module AHBUart #(
       wFIFOCount <= 0;
       wFIFOMaxIndex <= 0;
       wFIFO <= '{default: 0};
-    end
-
-    if (bp.wen) begin
+    end else if (bp.wen) begin
       case (bp.addr)
         TX_STATE: begin
           if (bp.strobe[2]) rate[7:0] <= bpData[2];