Provides several configurations of VexRISC as FeatherweightIP packages
VexRISC is a SpinalHDL-based RISC-V core generator. It is available under the MIT license. The source repository is here: https://github.com/SpinalHDL/VexRiscv
The fwvexrisc project contains several configurations of VexRISC as generated Verilog output with appropriate Featherweight-IP interfaces and debug infrastructure.