DoxyGen: typo corrections in Core

CMSIS/DoxyGen/Core/src/Ref_CompilerControl.txt

@@ -449,7 +449,7 @@ void Reset_Handler(void)
 /**************************************************************************************************/
 /**
 \def __INITIAL_SP
-\brief Compiler/linker symbol specifiying the location of the main stack (MSP).
+\brief Compiler/linker symbol specifying the location of the main stack (MSP).
 \details
 The address of the specified symbol is used to initialize the main stack pointer (MSP) during low
 level init. This is compiler/linker specific. CMSIS specifies common default for supported compilers. 
@@ -461,7 +461,7 @@ level init. This is compiler/linker specific. CMSIS specifies common default for
 /**************************************************************************************************/
 /**
 \def __STACK_LIMIT
-\brief Compiler/linker symbol specifiying the limit of the main stack (MSP).
+\brief Compiler/linker symbol specifying the limit of the main stack (MSP).
 \details
 The address of the specified symbol is used to initialize the main stack pointer limit (MSPLIM on Armv8-M)
 during low level init. This is compiler/linker specific. CMSIS specifies common default for supported

CMSIS/DoxyGen/Core/src/Ref_CoreReg.txt

@@ -92,7 +92,7 @@ void __set_CONTROL(uint32_t control);
     The function reads the Interrupt Program Status Register (IPSR) using the instruction \b MRS. 
     \n\n
     The ISPR contains the exception type number of the current Interrupt Service Routine (ISR). 
-    Each exception has an assocciated unique IRQn number. The following bits are used:
+    Each exception has an associated unique IRQn number. The following bits are used:
 
     - \b ISR_NUMBER (IPSR[8:0])
         - =0 Thread mode
@@ -149,7 +149,7 @@ uint32_t __get_IPSR(void);
         - =1 A signed overflow occurred (for signed additions or subtractions).
     \n\n
     - \b Q (APSR[27]) (DSP overflow or saturation flag) [not Cortex-M0]
-        - This flag is a \em sticky flag. Saturating and certain mutliplying instructions can set the
+        - This flag is a \em sticky flag. Saturating and certain multiplying instructions can set the
         flag, but cannot clear it. 
         - =1 When saturation or an overflow occurred.
     \n\n
@@ -374,7 +374,7 @@ uint32_t __get_PRIMASK(void);
         - When set, PRIMASK effectively changes the current priority level to 0. 
         This is the highest programmable level.
         - When set and a fault occurs, the hard fault handler will be executed.
-        - Useful for temprorarily disabling all interrupts for timing critical tasks. 
+        - Useful for temporarily disabling all interrupts for timing critical tasks. 
         - Does not have the ability to mask BusFault or bypass MPU.
 
     \sa 
@@ -485,7 +485,7 @@ uint32_t __get_FAULTMASK(void);
     FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrupt (NMI).
     FAULTMASK can be used to escalate a configurable fault handler (BusFault, usage fault, or 
     memory management fault) to hard fault level without invoking a hard fault. This allows the 
-    fault handler to pretend to be the hard fault handler, whith the ability to:
+    fault handler to pretend to be the hard fault handler, with the ability to:
     -# <b>Mask BusFault</b> by setting the BFHFNMIGN in the Configuration Control register.
     It can be used to test the bus system without causing a lockup. 
     -# <b>Bypass the MPU</b>, allowing accessing the MPU protected memory location without 
@@ -693,7 +693,7 @@ void __disable_fault_irq(void);
 
   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
   \return               PSPLIM Register value
-  \note    Only availabe for Armv8-M Architecture. 
+  \note    Only available for Armv8-M Architecture. 
  */
 uint32_t __get_PSPLIM(void);
 
@@ -705,7 +705,7 @@ uint32_t __get_PSPLIM(void);
 
   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
-  \note    Only availabe for Armv8-M Architecture. 
+  \note    Only available for Armv8-M Architecture. 
  */
 void __set_PSPLIM(uint32_t ProcStackPtrLimit);
 
@@ -717,7 +717,7 @@ void __set_PSPLIM(uint32_t ProcStackPtrLimit);
 
   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
   \return               MSPLIM Register value
-  \note    Only availabe for Armv8-M Architecture. 
+  \note    Only available for Armv8-M Architecture. 
  */
 uint32_t __get_MSPLIM(void);
 
@@ -729,7 +729,7 @@ uint32_t __get_MSPLIM(void);
 
   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
-  \note    Only availabe for Armv8-M Architecture. 
+  \note    Only available for Armv8-M Architecture. 
  */
 __set_MSPLIM(uint32_t MainStackPtrLimit);
 

CMSIS/DoxyGen/Core/src/Ref_NVIC.txt

@@ -296,8 +296,8 @@ uint32_t active;                                            /* Variable to store
 
 void TIMER0_IRQHandler(void)  {                             /* Timer 0 interrupt handler  */
 
-  if (LPC_TIM0->IR & (1 << 0))  {                           /* Check if interrupt for match channel 0 occured */ 
-    LPC_TIM0->IR |= (1 << 0);                               /* Acknowledge interrupt for match channel 0 occured */
+  if (LPC_TIM0->IR & (1 << 0))  {                           /* Check if interrupt for match channel 0 occurred */ 
+    LPC_TIM0->IR |= (1 << 0);                               /* Acknowledge interrupt for match channel 0 occurred */
   }
   active = NVIC_GetActive(TIMER0_IRQn);                     /* Get interrupt active state of timer 0 */
 }
@@ -598,7 +598,7 @@ void NVIC_ClearPendingIRQ(IRQn_Type IRQn);
         - IRQn must not be negative.
         - Each external interrupt has an active status bit. When the processor starts the interrupt 
         handler the bit is set to 1 and cleared when the interrupt return is executed.
-        - When an ISR is preempted and the processor executes anohter interrupt handler, the 
+        - When an ISR is preempted and the processor executes another interrupt handler, the 
         previous interrupt is still defined as active.
 
     \sa     
@@ -638,8 +638,8 @@ uint32_t NVIC_GetActive(IRQn_Type IRQn);
     - <b>For Cortex-M3, Cortex-M4, and Cortex-M7</b>: 
         - Dynamic switching of interrupt priority levels is supported.
         - Supports 0 to 255 priority levels.
-        - Priority-level registers have a maximum width of 8 bits and a minumum of 3 bits.
-        Each register can be further devided into preempt priority level and subpriority level.
+        - Priority-level registers have a maximum width of 8 bits and a minimum of 3 bits.
+        Each register can be further divided into preempt priority level and subpriority level.
 
     \sa     
         - \ref NVIC_GetPriority;  NVIC_SetPriorityGrouping; __set_BASEPRI;

CMSIS/DoxyGen/Core/src/Ref_SystemAndClock.txt

@@ -17,8 +17,8 @@ a more flexible configuration of the microcontroller system.
 \note Please pay special attention to the static variable \c SystemCoreClock. This variable might be
 used throughout the whole system initialization and runtime to calculate frequency/time related values.
 Thus one must assure that the variable always reflects the actual system clock speed. Be aware that
-a value stored to \c SystemCoreClock during low level initializaton (i.e. \c SystemInit()) might get
-overwritten by C libray startup code and/or .bss section initialization.
+a value stored to \c SystemCoreClock during low level initialization (i.e. \c SystemInit()) might get
+overwritten by C library startup code and/or .bss section initialization.
 Thus its highly recommended to call \ref SystemCoreClockUpdate at the beginning of the user \c main() routine.
 
 

CMSIS/DoxyGen/Core/src/Ref_Trustzone.txt

@@ -401,7 +401,7 @@ void __TZ_set_STACKSEAL_S (uint32_t *stackTop);
 
 /**
 \def __STACK_SEAL
-\brief Compiler/linker symbol specifiying the location of the stack seal.
+\brief Compiler/linker symbol specifying the location of the stack seal.
 \details
 The address of the specified symbol is used to set the stack seal during low level init.
 This is compiler/linker specific. CMSIS specifies common default for supported compilers. 

CMSIS/DoxyGen/Core/src/Ref_cmInstr.txt

@@ -361,7 +361,7 @@ void __STRT(uint32_t value, uint32_t ptr);
   \details Executes a LDAB instruction for 8 bit value.
   \param [in]    ptr  Pointer to data
   \return             value of type uint8_t at (*ptr)
-  \note    Only availabe for Armv8-M Architecture. 
+  \note    Only available for Armv8-M Architecture. 
  */
 uint8_t __LDAB(volatile uint8_t *ptr);
 
@@ -370,7 +370,7 @@ uint8_t __LDAB(volatile uint8_t *ptr);
   \details Executes a LDAH instruction for 16 bit values.
   \param [in]    ptr  Pointer to data
   \return        value of type uint16_t at (*ptr)
-  \note    Only availabe for Armv8-M Architecture. 
+  \note    Only available for Armv8-M Architecture. 
  */
 uint16_t __LDAH(volatile uint16_t *ptr);
 
@@ -379,7 +379,7 @@ uint16_t __LDAH(volatile uint16_t *ptr);
   \details Executes a LDA instruction for 32 bit values.
   \param [in]    ptr  Pointer to data
   \return        value of type uint32_t at (*ptr)
-  \note    Only availabe for Armv8-M Architecture. 
+  \note    Only available for Armv8-M Architecture. 
  */
 uint32_t __LDA(volatile uint32_t *ptr);
 
@@ -388,7 +388,7 @@ uint32_t __LDA(volatile uint32_t *ptr);
   \details Executes a STLB instruction for 8 bit values.
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
-  \note    Only availabe for Armv8-M Architecture. 
+  \note    Only available for Armv8-M Architecture. 
  */
 void __STLB(uint8_t value, volatile uint8_t *ptr);
 
@@ -397,7 +397,7 @@ void __STLB(uint8_t value, volatile uint8_t *ptr);
   \details Executes a STLH instruction for 16 bit values.
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
-  \note    Only availabe for Armv8-M Architecture. 
+  \note    Only available for Armv8-M Architecture. 
  */
 void __STLH(uint16_t value, volatile uint16_t *ptr);
 
@@ -406,7 +406,7 @@ void __STLH(uint16_t value, volatile uint16_t *ptr);
   \details Executes a STL instruction for 32 bit values.
   \param [in]  value  Value to store
   \param [in]    ptr  Pointer to location
-  \note    Only availabe for Armv8-M Architecture. 
+  \note    Only available for Armv8-M Architecture. 
  */
 void __STL(uint32_t value, volatile uint32_t *ptr);
 
@@ -415,7 +415,7 @@ void __STL(uint32_t value, volatile uint32_t *ptr);
   \details Executes a LDAB exclusive instruction for 8 bit value.
   \param [in]    ptr  Pointer to data
   \return             value of type uint8_t at (*ptr)
-  \note    Only availabe for Armv8-M Architecture. 
+  \note    Only available for Armv8-M Architecture. 
  */
 uint8_t __LDAEXB(volatile uint32_t *ptr);
 
@@ -424,7 +424,7 @@ uint8_t __LDAEXB(volatile uint32_t *ptr);
   \details Executes a LDAH exclusive instruction for 16 bit values.
   \param [in]    ptr  Pointer to data
   \return        value of type uint16_t at (*ptr)
-  \note    Only availabe for Armv8-M Architecture. 
+  \note    Only available for Armv8-M Architecture. 
  */
 uint16_t __LDAEXH(volatile uint32_t *ptr);
 
@@ -433,7 +433,7 @@ uint16_t __LDAEXH(volatile uint32_t *ptr);
   \details Executes a LDA exclusive instruction for 32 bit values.
   \param [in]    ptr  Pointer to data
   \return        value of type uint32_t at (*ptr)
-  \note    Only availabe for Armv8-M Architecture. 
+  \note    Only available for Armv8-M Architecture. 
  */
 uint32_t __LDAEX(volatile uint32_t *ptr);
 
@@ -444,7 +444,7 @@ uint32_t __LDAEX(volatile uint32_t *ptr);
   \param [in]    ptr  Pointer to location
   \return          0  Function succeeded
   \return          1  Function failed
-  \note    Only availabe for Armv8-M Architecture. 
+  \note    Only available for Armv8-M Architecture. 
  */
 uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr);
 
@@ -455,7 +455,7 @@ uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr);
   \param [in]    ptr  Pointer to location
   \return          0  Function succeeded
   \return          1  Function failed
-  \note    Only availabe for Armv8-M Architecture. 
+  \note    Only available for Armv8-M Architecture. 
  */
 uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr);
 
@@ -466,7 +466,7 @@ uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr);
   \param [in]    ptr  Pointer to location
   \return          0  Function succeeded
   \return          1  Function failed
-  \note    Only availabe for Armv8-M Architecture. 
+  \note    Only available for Armv8-M Architecture. 
  */
 uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr);
 

CMSIS/DoxyGen/Core/src/core_cm7.txt

@@ -144,7 +144,7 @@ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void);
   \param[in]   addr    address (aligned to 32-byte boundary)
   \param[in]   dsize   size of memory block (in number of bytes)
 
-  The function invalidates a memory block of size \em dsize [bytes] starting at address \em address. The address is aligned to 32-byte boundry.
+  The function invalidates a memory block of size \em dsize [bytes] starting at address \em address. The address is aligned to 32-byte boundary.
 */
 __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize);
 
@@ -154,7 +154,7 @@ __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t
   \param[in]   addr    address (aligned to 32-byte boundary)
   \param[in]   dsize   size of memory block (in number of bytes)
 
-  The function cleans a memory block of size \em dsize [bytes] starting at address \em address. The address is aligned to 32-byte boundry.
+  The function cleans a memory block of size \em dsize [bytes] starting at address \em address. The address is aligned to 32-byte boundary.
 
 
 */
@@ -166,7 +166,7 @@ __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize
   \param[in]   addr    address (aligned to 32-byte boundary)
   \param[in]   dsize   size of memory block (in number of bytes)
 
-  The function invalidates and cleans a memory block of size \em dsize [bytes] starting at address \em address. The address is aligned to 32-byte boundry.
+  The function invalidates and cleans a memory block of size \em dsize [bytes] starting at address \em address. The address is aligned to 32-byte boundary.
 */
 __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize);