Investigating the use of hint bits in JUMP statements for pipelined CPU branch predictors
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Updated
Oct 6, 2022
Investigating the use of hint bits in JUMP statements for pipelined CPU branch predictors
Standard five-stage pipelined 32-bit MIPS processor with hazard detection
A set of pipelined calculators for computing various complex mathematical functions
Crane Game using Custom Pipelined Processor
High-level block designs for MIPS 32 bit processor with pipelining & forwarding controls, hazard detection, and timing. Tested and verified in course on organization of computers.
Structure of Computer Systems course (3rd year, 1st semester)
Repository for the course project done as part of CS-230 (Digital Logic Design & Computer Architecture) course at IIT Bombay in Spring 2022.
Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor
Laboratorio 2 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
Vector ASIP for the application of filters to an image 🖼️
5-stage pipelined microprocessor with data forwarding, hazard detection and dynamic branch prediction written in VHDL
The IPPro is a 16-bit signed fixed-point, five-stage balanced pipelined RISC architecture that exploits the DSP48E1 features and provides balance among performance, latency and efficient resource utilization.
MIPS 32 bit processor - fully functional shared memory dual-core processor with MSI for cache coherency
Laboratorios, prácticos y teóricos de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
5 stages RISC pipelined processor with multiple instructions implemented in verilog including ALU Operations, Interrupts as a state machine, Jumps and branching instructions, Memory operations and more.. following Harvard architecture.
This repository is created to build a single cycle processor and converting it to a 5-stage pipelined processor capable of executing a bubble sort program.
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