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Because current commercially available computer systems provide cache coherence, if a group of CPUs all do concurrent non-atomic stores to a single variable, the series of values seen by all CPUs will be consistent with at least one global ordering.
Please note well that this section applies only when all CPUs’ accesses are to one single variable. In this single-variable case, cache coherence guarantees the global ordering, at least assuming that some of the more aggressive compiler optimizations are disabled via the Linux kernel’s ACCESS_ONCE() directive or C++11’s relaxed atomics [Bec11]. In contrast, if there are multiple variables, memory barriers are required for the CPUs to consistently agree on the order for current commercially available computer systems.
来自: Is Parallel Programming Hard, And, If So, What Can You Do About It?
我们能信任的东西
即所有CPU(不同架构)均遵从的准则:
第二条有意思,暂时不太准确理解其意思。几句耐人寻味的原文摘抄过来:
最后一句话,如果是对多个变量进行操作,那么需要memory barrier,换句话说,如果只有一个变量,无需memory barrier.
锁的内存屏障作用
锁的加锁和解锁操作必定以显性或隐性的方式存在memory barrier,这提供了内存顺序保证:第一个线程在临界区内的操作必定发生在第二个线程获得锁之前。Java的ReentrantLock的实现参考 #9
关于内存屏障不能做的假设
种类
屏障对
内存屏障必须成对使用才能推导出先后顺序。
从CPU的角度看为什么需要内存屏障
MESI
CPU使用MESI协议(或其升级款)来保证其缓存的一致性。当CPU进行数据写入时,如果数据不在当前核心,那么会发送Read Invalidate消息,指示其它核心将此数据置为无效状态并发送给当前核心。
详解
直接参考书中附录B
概括
写内存屏障作用于store buffer,读屏障作用于无效队列,完整的屏障同时作用于两者
总结
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