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hash_amd64.s
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/*
MIT License
Copyright (c) 2021 Prysmatic Labs
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
This code is based on Intel's implementation found in
https://github.com/intel/intel-ipsec-mb
Copied parts are
Copyright (c) 2012-2021, Intel Corporation
*/
#include "textflag.h"
// AVX x1 definitions
#define OUTPUT_PTR DI
#define DATA_PTR SI
#define NUM_BLKS DX
#define TBL CX
#define RAL AX
#define RBL BX
#define RCL BP
#define RDL R8
#define REL R9
#define RFL R10
#define RGL R11
#define RHL R12
#define XTMP0 X4
#define XTMP1 X5
#define XTMP2 X6
#define XTMP3 X7
#define XTMP4 X8
#define XTMP5 X11
#define XFER X9
#define y0 R13
#define y1 R14
#define y2 R15
#define _SHUF_00BA X10
#define _SHUF_DC00 X12
#define _BYTE_FLIP_MASK X13
#define COPY_XMM_AND_BSWAP(dst,src,msk) \
VMOVDQU src, dst; \
VPSHUFB msk, dst, dst
#define FOUR_ROUNDS_AND_SCHEDA(a, b, c, d, e, f, g, h, X0_, X1_, X2_, X3_) \
RORXL $(25-11), e, y0; \
VPALIGNR $4, X2_, X3_, XTMP0; \
RORXL $(22-13), a, y1; \
XORL e, y0; \
MOVL f, y2; \
RORXL $(11-6), y0, y0; \
XORL a, y1; \
XORL g, y2; \
VPADDD X0_, XTMP0, XTMP0; \
XORL e, y0; \
ANDL e, y2; \
RORXL $(13-2), y1, y1; \
VPALIGNR $4, X0_, X1_, XTMP1; \
XORL a, y1; \
RORXL $6, y0, y0; \
XORL g, y2; \
RORXL $2, y1, y1; \
ADDL y0, y2; \
ADDL (0*4)(SP), y2; \
MOVL a, y0; \
ADDL y2, h; \
MOVL a, y2; \
VPSRLD $7, XTMP1, XTMP2; \
ORL c, y0; \
ADDL h, d; \
ANDL c, y2; \
VPSLLD $(32-7), XTMP1, XTMP3; \
ANDL b, y0; \
ADDL y1, h; \
VPOR XTMP2, XTMP3, XTMP3; \
ORL y2, y0; \
ADDL y0, h
#define FOUR_ROUNDS_AND_SCHEDB(a, b, c, d, e, f, g, h, X0_, X1_, X2_, X3_) \
RORXL $(25-11), e, y0; \
RORXL $(22-13), a, y1; \
XORL e, y0; \
VPSRLD $18, XTMP1, XTMP2; \
MOVL f, y2; \
RORXL $(11-6), y0, y0; \
XORL a, y1; \
XORL g, y2; \
VPSRLD $3, XTMP1, XTMP4; \
XORL e, y0; \
ANDL e, y2; \
RORXL $(13-2), y1, y1; \
XORL a, y1; \
RORXL $6, y0, y0; \
VPSLLD $(32-18), XTMP1, XTMP1; \
XORL g, y2; \
RORXL $2, y1, y1; \
VPXOR XTMP1, XTMP3, XTMP3; \
ADDL y0, y2; \
ADDL (1*4)(SP), y2; \
MOVL a, y0; \
VPXOR XTMP2, XTMP3, XTMP3; \
ADDL y2, h; \
MOVL a, y2; \
ORL c, y0; \
VPXOR XTMP4, XTMP3, XTMP1; \
ADDL h, d; \
ANDL c, y2; \
VPSHUFD $0xFA, X3_, XTMP2; \
ANDL b, y0; \
ADDL y1, h; \
VPADDD XTMP1, XTMP0, XTMP0; \
ORL y2, y0; \
ADDL y0, h
#define FOUR_ROUNDS_AND_SCHEDC(a, b, c, d, e, f, g, h, X0_, X1_, X2_, X3_) \
RORXL $(25-11), e, y0; \
RORXL $(22-13), a, y1; \
XORL e, y0; \
VPSRLD $10, XTMP2, XTMP4; \
MOVL f, y2; \
RORXL $(11-6), y0, y0; \
XORL a, y1; \
VPSRLQ $19, XTMP2, XTMP3; \
XORL g, y2; \
XORL e, y0; \
ANDL e, y2; \
VPSRLQ $17, XTMP2, XTMP2; \
RORXL $(13-2), y1, y1; \
XORL a, y1; \
RORXL $6, y0, y0; \
VPXOR XTMP3, XTMP2, XTMP2; \
XORL g, y2; \
RORXL $2, y1, y1; \
ADDL y0, y2; \
VPXOR XTMP2, XTMP4, XTMP4; \
ADDL (2*4)(SP), y2; \
MOVL a, y0; \
ADDL y2, h; \
VPSHUFB _SHUF_00BA, XTMP4, XTMP4; \
MOVL a, y2; \
ORL c, y0; \
ADDL h, d; \
VPADDD XTMP4, XTMP0, XTMP0; \
ANDL c, y2; \
ANDL b, y0; \
VPSHUFD $0x50, XTMP0, XTMP2; \
ADDL y1, h; \
ORL y2, y0; \
ADDL y0, h
#define FOUR_ROUNDS_AND_SCHEDD(a, b, c, d, e, f, g, h, X0_, X1_, X2_, X3_) \
RORXL $(25-11), e, y0; \
RORXL $(22-13), a, y1; \
VPSRLD $10, XTMP2, XTMP5; \
XORL e, y0; \
MOVL f, y2; \
RORXL $(11-6), y0, y0; \
VPSRLQ $19, XTMP2, XTMP3; \
XORL a, y1; \
XORL g, y2; \
XORL e, y0; \
VPSRLQ $17, XTMP2, XTMP2; \
ANDL e, y2; \
RORXL $(13-2), y1, y1; \
XORL a, y1; \
VPXOR XTMP3, XTMP2, XTMP2; \
RORXL $6, y0, y0; \
XORL g, y2; \
RORXL $2, y1, y1; \
VPXOR XTMP2, XTMP5, XTMP5; \
ADDL y0, y2; \
ADDL (3*4)(SP), y2; \
MOVL a, y0; \
ADDL y2, h; \
MOVL a, y2; \
VPSHUFB _SHUF_DC00, XTMP5, XTMP5; \
ORL c, y0; \
ADDL h, d; \
ANDL c, y2; \
VPADDD XTMP0, XTMP5, X0_; \
ANDL b, y0; \
ADDL y1, h; \
ORL y2, y0; \
ADDL y0, h
#define FOUR_ROUNDS_AND_SCHED(a, b, c, d, e, f, g, h, X0_, X1_, X2_, X3_) \
FOUR_ROUNDS_AND_SCHEDA(a, b, c, d, e, f, g, h, X0_, X1_, X2_, X3_); \
FOUR_ROUNDS_AND_SCHEDB(h, a, b, c, d, e, f, g, X0_, X1_, X2_, X3_); \
FOUR_ROUNDS_AND_SCHEDC(g, h, a, b, c, d, e, f, X0_, X1_, X2_, X3_); \
FOUR_ROUNDS_AND_SCHEDD(f, g, h, a, b, c, d, e, X0_, X1_, X2_, X3_)
#define DO_ROUND(base, offset, a, b, c, d, e, f, g, h) \
RORXL $(25-11), e, y0; \
RORXL $(22-13), a, y1; \
XORL e, y0; \
MOVL f, y2; \
RORXL $(11-6), y0, y0; \
XORL a, y1; \
XORL g, y2; \
XORL e, y0; \
ANDL e, y2; \
RORXL $(13-2), y1, y1; \
XORL a, y1; \
RORXL $6, y0, y0; \
XORL g, y2; \
RORXL $2, y1, y1; \
ADDL y0, y2; \
ADDL (offset)(base), y2; \
MOVL a, y0; \
ADDL y2, h; \
MOVL a, y2; \
ORL c, y0; \
ADDL h, d; \
ANDL c, y2; \
ANDL b, y0; \
ADDL y1, h; \
ORL y2, y0; \
ADDL y0, h
// AVX x4 definitions
#define XA0 X8
#define XA1 X9
#define XA2 X10
#define XT0 X14
#define XT1 X13
#define XT2 X12
#define XT3 X11
#define XT4 X10
#define XT5 X9
#define TMP4 X15
#define TRANSPOSE_4_U32(r0, r1, r2, r3, t0, t1) \
VSHUFPS $0x44, r1, r0, t0; \
VSHUFPS $0xEE, r1, r0, r0; \
VSHUFPS $0x44, r3, r2, t1; \
VSHUFPS $0xEE, r3, r2, r2; \
VSHUFPS $0xDD, t1, t0, r1; \
VSHUFPS $0xDD, r2, r0, r3; \
VSHUFPS $0x88, r2, r0, r0; \
VSHUFPS $0x88, t1, t0, t0
#define PRORD4(src, imm) \
VPSLLD $(32 - imm), src, TMP4; \
VPSRLD $imm, src, src; \
VPOR TMP4, src, src
#define PRORD4_nd(dst, src, amt) \
VPSLLD $(32 - amt), src, TMP4; \
VPSRLD $amt, src, dst; \
VPOR TMP4, dst, dst
#define ROUND4_00_15_PADD(a, b, c, d, e, f, g, h, T1, i) \
PRORD4_nd(XA0, e, 5); \
VPXOR g, f, XA2; \
VPAND e, XA2, XA2; \
VPXOR g, XA2, XA2; \
PRORD4_nd(XA1, e, 25); \
VMOVDQU (64*i)(TBL), T1; \
VPXOR e, XA0, XA0; \
PRORD4(XA0, 6); \
VPADDD XA2, h, h; \
PRORD4_nd(XA2, a, 11); \
VPADDD T1, h, h; \
VPXOR XA1, XA0, XA0; \
PRORD4_nd(XA1, a, 22); \
VPXOR c, a, T1; \
VPAND b, T1, T1; \
VPADDD XA0, h, h; \
VPADDD h, d, d; \
VPXOR a, XA2, XA2; \
PRORD4(XA2, 2); \
VPXOR XA1, XA2, XA2; \
VPAND c, a, XA1; \
VPOR T1, XA1, XA1; \
VPADDD XA1, h, h; \
VPADDD XA2, h, h
#define ROUND4_00_15(a, b, c, d, e, f, g, h, T1, i) \
PRORD4_nd(XA0, e, 5); \
VPXOR g, f, XA2; \
VPAND e, XA2, XA2; \
VPXOR g, XA2, XA2; \
PRORD4_nd(XA1, e, 25); \
VMOVDQU T1, (16*(i&0xf))(SP); \
VPADDD (64*i)(TBL), T1, T1; \
VPXOR e, XA0, XA0; \
PRORD4(XA0, 6); \
VPADDD XA2, h, h; \
PRORD4_nd(XA2, a, 11); \
VPADDD T1, h, h; \
VPXOR XA1, XA0, XA0; \
PRORD4_nd(XA1, a, 22); \
VPXOR c, a, T1; \
VPAND b, T1, T1; \
VPADDD XA0, h, h; \
VPADDD h, d, d; \
VPXOR a, XA2, XA2; \
PRORD4(XA2, 2); \
VPXOR XA1, XA2, XA2; \
VPAND c, a, XA1; \
VPOR T1, XA1, XA1; \
VPADDD XA1, h, h; \
VPADDD XA2, h, h
#define ROUND4_16_XX(a, b, c, d, e, f, g, h, T1, i) \
VMOVDQU (16*((i-15)&0x0f))(SP), T1; \
VMOVDQU (16*((i-2)&0x0f))(SP), XA1; \
VMOVDQA T1, XA0; \
PRORD4(T1, 11); \
VMOVDQA XA1, XA2; \
PRORD4(XA1, 2); \
VPXOR XA0, T1, T1; \
PRORD4(T1, 7); \
VPXOR XA2, XA1, XA1; \
PRORD4(XA1, 17); \
VPSRLD $3, XA0, XA0; \
VPXOR XA0, T1, T1; \
VPSRLD $10, XA2, XA2; \
VPXOR XA2, XA1, XA1; \
VPADDD (16*((i-16)&0x0f))(SP), T1, T1; \
VPADDD (16*((i-7)&0x0f))(SP), XA1, XA1; \
VPADDD XA1, T1, T1; \
ROUND4_00_15(a, b, c, d, e, f, g, h, T1, i)
// AVX2 x8 definitions
#define a0 Y12
#define a1 Y13
#define a2 Y14
#define TMP Y15
#define TMP0 Y6
#define TMP1 Y7
#define TT0 Y8
#define TT1 Y9
#define TT2 Y10
#define TT3 Y11
#define TT4 Y12
#define TT5 Y13
#define TT6 Y14
#define TT7 Y15
#define _DIGEST 512
#define _YTMP 768
#define YTMP0 _YTMP + 0*32
#define YTMP1 _YTMP + 1*32
#define YTMP2 _YTMP + 2*32
#define YTMP3 _YTMP + 3*32
#define TRANSPOSE8_U32_LOAD8(offset) \
VMOVUPS (offset + 0*64)(DATA_PTR), TT0; \
VMOVUPS (offset + 1*64)(DATA_PTR), TT1; \
VMOVUPS (offset + 2*64)(DATA_PTR), TT2; \
VMOVUPS (offset + 3*64)(DATA_PTR), TT3; \
VMOVUPS (offset + 0*64+16)(DATA_PTR), TT4; \
VMOVUPS (offset + 1*64+16)(DATA_PTR), TT5; \
VMOVUPS (offset + 2*64+16)(DATA_PTR), TT6; \
VMOVUPS (offset + 3*64+16)(DATA_PTR), TT7; \
VINSERTI128 $0x01, (offset + 4*64)(DATA_PTR), TT0, TT0; \
VINSERTI128 $0x01, (offset + 5*64)(DATA_PTR), TT1, TT1; \
VINSERTI128 $0x01, (offset + 6*64)(DATA_PTR), TT2, TT2; \
VINSERTI128 $0x01, (offset + 7*64)(DATA_PTR), TT3, TT3; \
VINSERTI128 $0x01, (offset + 4*64+16)(DATA_PTR), TT4, TT4; \
VINSERTI128 $0x01, (offset + 5*64+16)(DATA_PTR), TT5, TT5; \
VINSERTI128 $0x01, (offset + 6*64+16)(DATA_PTR), TT6, TT6; \
VINSERTI128 $0x01, (offset + 7*64+16)(DATA_PTR), TT7, TT7
#define TRANSPOSE8_U32_PRELOADED \
VSHUFPS $0x44, TT1, TT0, TMP0; \
VSHUFPS $0xEE, TT1, TT0, TT0; \
VSHUFPS $0x44, TT3, TT2, TMP1; \
VSHUFPS $0xEE, TT3, TT2, TT2; \
VSHUFPS $0xDD, TMP1, TMP0, TT1; \
VSHUFPS $0xDD, TT2, TT0, TT3; \
VSHUFPS $0x88, TT2, TT0, TT2; \
VSHUFPS $0x88, TMP1, TMP0, TT0; \
VSHUFPS $0x44, TT5, TT4, TMP0; \
VSHUFPS $0xEE, TT5, TT4, TT4; \
VSHUFPS $0x44, TT7, TT6, TMP1; \
VSHUFPS $0xEE, TT7, TT6, TT6; \
VSHUFPS $0xDD, TMP1, TMP0, TT5; \
VSHUFPS $0xDD, TT6, TT4, TT7; \
VSHUFPS $0x88, TT6, TT4, TT6; \
VSHUFPS $0x88, TMP1, TMP0, TT4
#define TRANSPOSE8_U32 \
VSHUFPS $0x44, Y1, Y0, TT0; \
VSHUFPS $0xEE, Y1, Y0, Y0; \
VSHUFPS $0x44, Y3, Y2, TT1; \
VSHUFPS $0xEE, Y3, Y2, Y2; \
VSHUFPS $0xDD, TT1, TT0, Y3; \
VSHUFPS $0x88, Y2, Y0, Y1; \
VSHUFPS $0xDD, Y2, Y0, Y0; \
VSHUFPS $0x88, TT1, TT0, TT0; \
VSHUFPS $0x44, Y5, Y4, Y2; \
VSHUFPS $0xEE, Y5, Y4, Y4; \
VSHUFPS $0x44, Y7, Y6, TT1; \
VSHUFPS $0xEE, Y7, Y6, Y6; \
VSHUFPS $0xDD, TT1, Y2, Y7; \
VSHUFPS $0x88, Y6, Y4, Y5; \
VSHUFPS $0xDD, Y6, Y4, Y4; \
VSHUFPS $0x88, TT1, Y2, TT1; \
VPERM2F128 $0x13, Y1, Y5, Y6; \
VPERM2F128 $0x02, Y1, Y5, Y2; \
VPERM2F128 $0x13, Y3, Y7, Y5; \
VPERM2F128 $0x02, Y3, Y7, Y1; \
VPERM2F128 $0x13, Y0, Y4, Y7; \
VPERM2F128 $0x02, Y0, Y4, Y3; \
VPERM2F128 $0x13, TT0, TT1, Y4; \
VPERM2F128 $0x02, TT0, TT1, Y0
#define PRORD(src, imm) \
VPSLLD $(32 - imm), src, TMP; \
VPSRLD $imm, src, src; \
VPOR TMP, src, src
#define PRORD_nd(dst, src, amt) \
VPSLLD $(32 - amt), src, TMP; \
VPSRLD $amt, src, dst; \
VPOR TMP, dst, dst
#define ROUND_00_15_PADD(a, b, c, d, e, f, g, h, T1, i) \
PRORD_nd(a0, e, 5); \
VPXOR g, f, a2; \
VPAND e, a2, a2; \
VPXOR g, a2, a2; \
PRORD_nd(a1, e, 25); \
VMOVDQU (64*i)(TBL), T1; \
VPXOR e, a0, a0; \
PRORD(a0, 6); \
VPADDD a2, h, h; \
PRORD_nd(a2, a, 11); \
VPADDD T1, h, h; \
VPXOR a1, a0, a0; \
PRORD_nd(a1, a, 22); \
VPXOR c, a, T1; \
VPAND b, T1, T1; \
VPADDD a0, h, h; \
VPADDD h, d, d; \
VPXOR a, a2, a2; \
PRORD(a2, 2); \
VPXOR a1, a2, a2; \
VPAND c, a, a1; \
VPOR T1, a1, a1; \
VPADDD a1, h, h; \
VPADDD a2, h, h
#define ROUND_00_15(a, b, c, d, e, f, g, h, T1, i) \
PRORD_nd(a0, e, 5); \
VPXOR g, f, a2; \
VPAND e, a2, a2; \
VPXOR g, a2, a2; \
PRORD_nd(a1, e, 25); \
VMOVDQU T1, (32*(i&0xf))(SP); \
VPADDD (64*i)(TBL), T1, T1; \
VPXOR e, a0, a0; \
PRORD(a0, 6); \
VPADDD a2, h, h; \
PRORD_nd(a2, a, 11); \
VPADDD T1, h, h; \
VPXOR a1, a0, a0; \
PRORD_nd(a1, a, 22); \
VPXOR c, a, T1; \
VPAND b, T1, T1; \
VPADDD a0, h, h; \
VPADDD h, d, d; \
VPXOR a, a2, a2; \
PRORD(a2, 2); \
VPXOR a1, a2, a2; \
VPAND c, a, a1; \
VPOR T1, a1, a1; \
VPADDD a1, h, h; \
VPADDD a2, h, h
#define ROUND_16_XX(a, b, c, d, e, f, g, h, T1, i) \
VMOVDQU (32*((i-15)&0x0f))(SP), T1; \
VMOVDQU (32*((i-2)&0x0f))(SP), a1; \
VMOVDQA T1, a0; \
PRORD(T1, 11); \
VMOVDQA a1, a2; \
PRORD(a1, 2); \
VPXOR a0, T1, T1; \
PRORD(T1, 7); \
VPXOR a2, a1, a1; \
PRORD(a1, 17); \
VPSRLD $3, a0, a0; \
VPXOR a0, T1, T1; \
VPSRLD $10, a2, a2; \
VPXOR a2, a1, a1; \
VPADDD (32*((i-16)&0x0f))(SP), T1, T1; \
VPADDD (32*((i-7)&0x0f))(SP), a1, a1; \
VPADDD a1, T1, T1; \
ROUND_00_15(a, b, c, d, e, f, g, h, T1, i)
// AVX x16 definitions
#define PADDINGAVX512 R8
#define DIGESTAVX512 R11
#define ZT1 Z8
#define ZTMP0 Z9
#define ZTMP1 Z10
#define ZTMP2 Z11
#define ZTMP3 Z12
#define ZTMP4 Z13
#define ZTMP5 Z14
#define ZTMP6 Z15
#define YW0 Y16
#define YW1 Y17
#define YW2 Y18
#define YW3 Y19
#define YW4 Y20
#define YW5 Y21
#define YW6 Y22
#define YW7 Y23
#define YW8 Y24
#define YW9 Y25
#define YW10 Y26
#define YW11 Y27
#define YW12 Y28
#define YW13 Y29
#define YW14 Y30
#define YW15 Y31
#define W0 Z16
#define W1 Z17
#define W2 Z18
#define W3 Z19
#define W4 Z20
#define W5 Z21
#define W6 Z22
#define W7 Z23
#define W8 Z24
#define W9 Z25
#define W10 Z26
#define W11 Z27
#define W12 Z28
#define W13 Z29
#define W14 Z30
#define W15 Z31
#define TRANSPOSE_8x16_U32 \
VMOVDQA32 ZTMP5, ZTMP0; \
VMOVDQA32 ZTMP5, ZTMP1; \
VPERMI2D Z4, Z0, ZTMP0; \
VPERMI2D Z5, Z1, ZTMP1; \
VMOVDQA32 ZTMP6, ZTMP2; \
VMOVDQA32 ZTMP6, ZTMP3; \
VPERMI2D Z4, Z0, ZTMP2; \
VPERMI2D Z5, Z1, ZTMP3; \
VMOVDQA32 ZTMP5, Z0; \
VMOVDQA32 ZTMP5, Z1; \
VPERMI2D Z6, Z2, Z0; \
VPERMI2D Z7, Z3, Z1; \
VMOVDQA32 ZTMP6, Z4; \
VMOVDQA32 ZTMP6, Z5; \
VPERMI2D Z6, Z2, Z4; \
VPERMI2D Z7, Z3, Z5; \
VSHUFPS $0x88, ZTMP1, ZTMP0, Z6; \
VSHUFPS $0xDD, ZTMP1, ZTMP0, Z7; \
VSHUFPS $0x88, ZTMP3, ZTMP2, ZTMP1; \
VSHUFPS $0xDD, ZTMP3, ZTMP2, ZTMP0; \
VSHUFPS $0x88, Z5, Z4, ZTMP2; \
VSHUFPS $0xDD, Z5, Z4, ZTMP3; \
VSHUFPS $0x88, Z1, Z0, Z4; \
VSHUFPS $0xDD, Z1, Z0, Z5; \
VMOVDQA32 ZTMP5, Z0; \
VMOVDQA32 ZTMP5, Z1; \
VPERMI2D Z4, Z6, Z0; \
VPERMI2D Z5, Z7, Z1; \
VMOVDQA32 ZTMP6, Z2; \
VMOVDQA32 ZTMP6, Z3; \
VPERMI2D Z4, Z6, Z2; \
VPERMI2D Z5, Z7, Z3; \
VMOVDQA32 ZTMP5, Z4; \
VMOVDQA32 ZTMP5, Z5; \
VPERMI2D ZTMP2, ZTMP1, Z4; \
VPERMI2D ZTMP3, ZTMP0, Z5; \
VMOVDQA32 ZTMP6, Z6; \
VMOVDQA32 ZTMP6, Z7; \
VPERMI2D ZTMP2, ZTMP1, Z6; \
VPERMI2D ZTMP3, ZTMP0, Z7
#define TRANSPOSE16_U32_PRELOADED \
VSHUFPS $0x44, W1, W0, ZTMP0; \
VSHUFPS $0xEE, W1, W0, W0; \
VSHUFPS $0x44, W3, W2, ZTMP1; \
VSHUFPS $0xEE, W3, W2, W2; \
VSHUFPS $0xDD, ZTMP1, ZTMP0, W3; \
VSHUFPS $0x88, W2, W0, W1; \
VSHUFPS $0xDD, W2, W0, W0; \
VSHUFPS $0x88, ZTMP1, ZTMP0, ZTMP0; \
VMOVDQU64 _PSHUFFLE_TRANSPOSE_MASK1<>(SB), ZTMP4; \
VMOVDQU64 _PSHUFFLE_TRANSPOSE_MASK2<>(SB), ZTMP5; \
VSHUFPS $0x44, W5, W4, W2; \
VSHUFPS $0xEE, W5, W4, W4; \
VSHUFPS $0x44, W7, W6, ZTMP1; \
VSHUFPS $0xEE, W7, W6, W6; \
VSHUFPS $0xDD, ZTMP1, W2, W7; \
VSHUFPS $0x88, W6, W4, W5; \
VSHUFPS $0xDD, W6, W4, W4; \
VSHUFPS $0x88, ZTMP1, W2, W2; \
VSHUFPS $0x44, W9, W8, W6; \
VSHUFPS $0xEE, W9, W8, W8; \
VSHUFPS $0x44, W11, W10, ZTMP1; \
VSHUFPS $0xEE, W11, W10, W10; \
VSHUFPS $0xDD, ZTMP1, W6, W11; \
VSHUFPS $0x88, W10, W8, W9; \
VSHUFPS $0xDD, W10, W8, W8; \
VSHUFPS $0x88, ZTMP1, W6, W6; \
VSHUFPS $0x44, W13, W12, W10; \
VSHUFPS $0xEE, W13, W12, W12; \
VSHUFPS $0x44, W15, W14, ZTMP1; \
VSHUFPS $0xEE, W15, W14, W14; \
VSHUFPS $0xDD, ZTMP1, W10, W15; \
VSHUFPS $0x88, W14, W12, W13; \
VSHUFPS $0xDD, W14, W12, W12; \
VSHUFPS $0x88, ZTMP1, W10, W10; \
VMOVDQU32 ZTMP4, ZTMP1; \
VPERMI2Q W13, W9, ZTMP1; \
VMOVDQU32 ZTMP5, W14; \
VPERMI2Q W13, W9, W14; \
VMOVDQU32 ZTMP4, W9; \
VPERMI2Q W15, W11, W9; \
VMOVDQU32 ZTMP5, W13; \
VPERMI2Q W15, W11, W13; \
VMOVDQU32 ZTMP4, W11; \
VPERMI2Q W12, W8, W11; \
VMOVDQU32 ZTMP5, W15; \
VPERMI2Q W12, W8, W15; \
VMOVDQU32 ZTMP4, W8; \
VPERMI2Q W10, W6, W8; \
VMOVDQU32 ZTMP5, W12; \
VPERMI2Q W10, W6, W12; \
VMOVDQU32 ZTMP1, W10; \
VMOVDQU32 ZTMP4, ZTMP1; \
VPERMI2Q W5, W1, ZTMP1; \
VMOVDQU32 ZTMP5, W6; \
VPERMI2Q W5, W1, W6; \
VMOVDQU32 ZTMP4, W1; \
VPERMI2Q W7, W3, W1; \
VMOVDQU32 ZTMP5, W5; \
VPERMI2Q W7, W3, W5; \
VMOVDQU32 ZTMP4, W3; \
VPERMI2Q W4, W0, W3; \
VMOVDQU32 ZTMP5, W7; \
VPERMI2Q W4, W0, W7; \
VMOVDQU32 ZTMP4, W0; \
VPERMI2Q W2, ZTMP0, W0; \
VMOVDQU32 ZTMP5, W4; \
VPERMI2Q W2, ZTMP0, W4; \
VMOVDQU32 ZTMP1, W2
#define PROCESS_LOOP_AVX512__(A, B, C, D, E, F, G, H, reg, WT) \
VMOVDQA32 E, ZTMP0; \
VPRORD $6, E, ZTMP1; \
VPRORD $11, E, ZTMP2; \
VPRORD $25, E, ZTMP3; \
VPTERNLOGD $0xCA, G, F, ZTMP0; \
VPADDD WT, reg, ZT1; \
VPTERNLOGD $0x96, ZTMP3, ZTMP2, ZTMP1; \
VPADDD ZTMP0, ZT1, ZT1; \
VPADDD ZTMP1, ZT1, ZT1; \
VPADDD ZT1, D, D; \
VPRORD $2, A, H; \
VPRORD $13, A, ZTMP2; \
VPRORD $22, A, ZTMP3; \
VMOVDQA32 A, ZTMP0; \
VPTERNLOGD $0xE8, C, B, ZTMP0; \
VPTERNLOGD $0x96, ZTMP3, ZTMP2, H; \
VPADDD ZTMP0, H, H; \
VPADDD ZT1, H, H
#define PROCESS_LOOP_AVX512(A, B, C, D, E, F, G, H, WT) \
VPADDD ZTMP3, H, ZT1; \
PROCESS_LOOP_AVX512__(A, B, C, D, E, F, G, H, ZT1, WT)
#define PROCESS_LOOP_PADDING_AVX512(A, B, C, D, E, F, G, H, WT) \
PROCESS_LOOP_AVX512__(A, B, C, D, E, F, G, H, H, WT)
#define MSG_SCHED_ROUND_16_63_AVX512(WT, WTp1, WTp9, WTp14) \
VPRORD $17, WTp14, ZTMP4; \
VPRORD $19, WTp14, ZTMP5; \
VPSRLD $10, WTp14, ZTMP6; \
VPTERNLOGD $0x96, ZTMP6, ZTMP5, ZTMP4; \
VPADDD ZTMP4, WT, WT; \
VPADDD WTp9, WT, WT; \
VPRORD $7, WTp1, ZTMP4; \
VPRORD $18, WTp1, ZTMP5; \
VPSRLD $3, WTp1, ZTMP6; \
VPTERNLOGD $0x96, ZTMP6, ZTMP5, ZTMP4; \
VPADDD ZTMP4, WT, WT
// Sha-ni definitions
#define SAVE_SP R8
#define SHA256PADDING CX
#define SHA256CONSTANTS AX
#define MSG X0
#define STATE0 X1
#define STATE1 X2
#define MSGTMP0 X3
#define MSGTMP1 X4
#define MSGTMP2 X5
#define MSGTMP3 X6
#define MSGTMP4 X7
#define SHUF_MASK X8
#define ABEF_SAVE X9
#define CDGH_SAVE X10
#define STATE0b X9
#define STATE1b X10
#define MSGTMP0b X11
#define MSGTMP1b X12
#define MSGTMP2b X13
#define MSGTMP3b X14
#define MSGTMP4b X15
#define ROUNDS_16_XX_SHA(T0, T1, T3, T4, S0, S1, i) \
VMOVDQA T0, MSG; \
PADDD (i*16)(SHA256CONSTANTS), MSG; \
SHA256RNDS2 X0, S0, S1; \
VMOVDQA T0, T4; \
PALIGNR $4, T3, T4; \
PADDD T4, T1; \
SHA256MSG2 T0, T1; \
VPSHUFD $0x0E, MSG, MSG; \
SHA256RNDS2 X0, S1, S0; \
SHA256MSG1 T0, T3
#define ROUND_PADD_SHA_x1(i) \
VMOVDQU (i*16)(SHA256PADDING), MSG; \
SHA256RNDS2 MSG, STATE0, STATE1; \
PSHUFD $0x0E, MSG, MSG; \
SHA256RNDS2 MSG, STATE1, STATE0
#define ROUND_PADD_SHA(i) \
VMOVDQU (i*16)(SHA256PADDING), MSG; \
SHA256RNDS2 MSG, STATE0, STATE1; \
SHA256RNDS2 MSG, STATE0b, STATE1b; \
PSHUFD $0x0E, MSG, MSG; \
SHA256RNDS2 MSG, STATE1, STATE0; \
SHA256RNDS2 MSG, STATE1b, STATE0b
TEXT ·_hash(SB), 0, $928-36
CMPB ·hasShani(SB), $1
JE shani
CMPB ·hasAVX512(SB), $1
JE avx512
CMPB ·hasAVX2(SB), $1
JE avx2
MOVQ digests+0(FP), OUTPUT_PTR // digests *[][32]byte
MOVQ p_base+8(FP), DATA_PTR // p [][32]byte
MOVL count+32(FP), NUM_BLKS // NUM_BLKS uint32
avx1:
CMPL NUM_BLKS, $4
JB avx1_x1
// Load pre-transposed digest
MOVQ $_DIGEST_16<>(SB), TBL
VMOVDQU (0*64)(TBL), X0
VMOVDQU (1*64)(TBL), X1
VMOVDQU (2*64)(TBL), X2
VMOVDQU (3*64)(TBL), X3
VMOVDQU (4*64)(TBL), X4
VMOVDQU (5*64)(TBL), X5
VMOVDQU (6*64)(TBL), X6
VMOVDQU (7*64)(TBL), X7
MOVQ $_K256_16<>(SB), TBL
// First 16 rounds
VMOVDQU _PSHUFFLE_BYTE_FLIP_MASK_16<>(SB), TMP4
VMOVUPS (0*64 + 0*16)(DATA_PTR), XT2
VMOVUPS (1*64 + 0*16)(DATA_PTR), XT1
VMOVUPS (2*64 + 0*16)(DATA_PTR), XT4
VMOVUPS (3*64 + 0*16)(DATA_PTR), XT3
TRANSPOSE_4_U32(XT2, XT1, XT4, XT3, XT0, XT5)
VPSHUFB TMP4, XT0, XT0
VPSHUFB TMP4, XT1, XT1
VPSHUFB TMP4, XT2, XT2
VPSHUFB TMP4, XT3, XT3
ROUND4_00_15(X0, X1, X2, X3, X4, X5, X6, X7, XT0, 0x0)
ROUND4_00_15(X7, X0, X1, X2, X3, X4, X5, X6, XT1, 0x1)
ROUND4_00_15(X6, X7, X0, X1, X2, X3, X4, X5, XT2, 0x2)
ROUND4_00_15(X5, X6, X7, X0, X1, X2, X3, X4, XT3, 0x3)
VMOVDQU _PSHUFFLE_BYTE_FLIP_MASK_16<>(SB), TMP4
VMOVUPS (0*64 + 1*16)(DATA_PTR), XT2
VMOVUPS (1*64 + 1*16)(DATA_PTR), XT1
VMOVUPS (2*64 + 1*16)(DATA_PTR), XT4
VMOVUPS (3*64 + 1*16)(DATA_PTR), XT3
TRANSPOSE_4_U32(XT2, XT1, XT4, XT3, XT0, XT5)
VPSHUFB TMP4, XT0, XT0
VPSHUFB TMP4, XT1, XT1
VPSHUFB TMP4, XT2, XT2
VPSHUFB TMP4, XT3, XT3
ROUND4_00_15(X4, X5, X6, X7, X0, X1, X2, X3, XT0, 0x4)
ROUND4_00_15(X3, X4, X5, X6, X7, X0, X1, X2, XT1, 0x5)
ROUND4_00_15(X2, X3, X4, X5, X6, X7, X0, X1, XT2, 0x6)
ROUND4_00_15(X1, X2, X3, X4, X5, X6, X7, X0, XT3, 0x7)
VMOVDQU _PSHUFFLE_BYTE_FLIP_MASK_16<>(SB), TMP4
VMOVUPS (0*64 + 2*16)(DATA_PTR), XT2
VMOVUPS (1*64 + 2*16)(DATA_PTR), XT1
VMOVUPS (2*64 + 2*16)(DATA_PTR), XT4
VMOVUPS (3*64 + 2*16)(DATA_PTR), XT3
TRANSPOSE_4_U32(XT2, XT1, XT4, XT3, XT0, XT5)
VPSHUFB TMP4, XT0, XT0
VPSHUFB TMP4, XT1, XT1
VPSHUFB TMP4, XT2, XT2
VPSHUFB TMP4, XT3, XT3
ROUND4_00_15(X0, X1, X2, X3, X4, X5, X6, X7, XT0, 0x8)
ROUND4_00_15(X7, X0, X1, X2, X3, X4, X5, X6, XT1, 0x9)
ROUND4_00_15(X6, X7, X0, X1, X2, X3, X4, X5, XT2, 0xa)
ROUND4_00_15(X5, X6, X7, X0, X1, X2, X3, X4, XT3, 0xb)
VMOVDQU _PSHUFFLE_BYTE_FLIP_MASK_16<>(SB), TMP4
VMOVUPS (0*64 + 3*16)(DATA_PTR), XT2
VMOVUPS (1*64 + 3*16)(DATA_PTR), XT1
VMOVUPS (2*64 + 3*16)(DATA_PTR), XT4
VMOVUPS (3*64 + 3*16)(DATA_PTR), XT3
TRANSPOSE_4_U32(XT2, XT1, XT4, XT3, XT0, XT5)
VPSHUFB TMP4, XT0, XT0
VPSHUFB TMP4, XT1, XT1
VPSHUFB TMP4, XT2, XT2
VPSHUFB TMP4, XT3, XT3
ROUND4_00_15(X4, X5, X6, X7, X0, X1, X2, X3, XT0, 0xc)
ROUND4_00_15(X3, X4, X5, X6, X7, X0, X1, X2, XT1, 0xd)
ROUND4_00_15(X2, X3, X4, X5, X6, X7, X0, X1, XT2, 0xe)
ROUND4_00_15(X1, X2, X3, X4, X5, X6, X7, X0, XT3, 0xf)
// Rounds 16-31
ROUND4_16_XX(X0, X1, X2, X3, X4, X5, X6, X7, XT0, 0x10)
ROUND4_16_XX(X7, X0, X1, X2, X3, X4, X5, X6, XT0, 0x11)
ROUND4_16_XX(X6, X7, X0, X1, X2, X3, X4, X5, XT0, 0x12)
ROUND4_16_XX(X5, X6, X7, X0, X1, X2, X3, X4, XT0, 0x13)
ROUND4_16_XX(X4, X5, X6, X7, X0, X1, X2, X3, XT0, 0x14)
ROUND4_16_XX(X3, X4, X5, X6, X7, X0, X1, X2, XT0, 0x15)
ROUND4_16_XX(X2, X3, X4, X5, X6, X7, X0, X1, XT0, 0x16)
ROUND4_16_XX(X1, X2, X3, X4, X5, X6, X7, X0, XT0, 0x17)
ROUND4_16_XX(X0, X1, X2, X3, X4, X5, X6, X7, XT0, 0x18)
ROUND4_16_XX(X7, X0, X1, X2, X3, X4, X5, X6, XT0, 0x19)
ROUND4_16_XX(X6, X7, X0, X1, X2, X3, X4, X5, XT0, 0x1a)
ROUND4_16_XX(X5, X6, X7, X0, X1, X2, X3, X4, XT0, 0x1b)
ROUND4_16_XX(X4, X5, X6, X7, X0, X1, X2, X3, XT0, 0x1c)
ROUND4_16_XX(X3, X4, X5, X6, X7, X0, X1, X2, XT0, 0x1d)
ROUND4_16_XX(X2, X3, X4, X5, X6, X7, X0, X1, XT0, 0x1e)
ROUND4_16_XX(X1, X2, X3, X4, X5, X6, X7, X0, XT0, 0x1f)
// Rounds 32--47
ROUND4_16_XX(X0, X1, X2, X3, X4, X5, X6, X7, XT0, 0x20)
ROUND4_16_XX(X7, X0, X1, X2, X3, X4, X5, X6, XT0, 0x21)
ROUND4_16_XX(X6, X7, X0, X1, X2, X3, X4, X5, XT0, 0x22)
ROUND4_16_XX(X5, X6, X7, X0, X1, X2, X3, X4, XT0, 0x23)
ROUND4_16_XX(X4, X5, X6, X7, X0, X1, X2, X3, XT0, 0x24)
ROUND4_16_XX(X3, X4, X5, X6, X7, X0, X1, X2, XT0, 0x25)
ROUND4_16_XX(X2, X3, X4, X5, X6, X7, X0, X1, XT0, 0x26)
ROUND4_16_XX(X1, X2, X3, X4, X5, X6, X7, X0, XT0, 0x27)
ROUND4_16_XX(X0, X1, X2, X3, X4, X5, X6, X7, XT0, 0x28)
ROUND4_16_XX(X7, X0, X1, X2, X3, X4, X5, X6, XT0, 0x29)
ROUND4_16_XX(X6, X7, X0, X1, X2, X3, X4, X5, XT0, 0x2a)
ROUND4_16_XX(X5, X6, X7, X0, X1, X2, X3, X4, XT0, 0x2b)
ROUND4_16_XX(X4, X5, X6, X7, X0, X1, X2, X3, XT0, 0x2c)
ROUND4_16_XX(X3, X4, X5, X6, X7, X0, X1, X2, XT0, 0x2d)
ROUND4_16_XX(X2, X3, X4, X5, X6, X7, X0, X1, XT0, 0x2e)
ROUND4_16_XX(X1, X2, X3, X4, X5, X6, X7, X0, XT0, 0x2f)
// Rounds 48--64
ROUND4_16_XX(X0, X1, X2, X3, X4, X5, X6, X7, XT0, 0x30)
ROUND4_16_XX(X7, X0, X1, X2, X3, X4, X5, X6, XT0, 0x31)
ROUND4_16_XX(X6, X7, X0, X1, X2, X3, X4, X5, XT0, 0x32)
ROUND4_16_XX(X5, X6, X7, X0, X1, X2, X3, X4, XT0, 0x33)
ROUND4_16_XX(X4, X5, X6, X7, X0, X1, X2, X3, XT0, 0x34)
ROUND4_16_XX(X3, X4, X5, X6, X7, X0, X1, X2, XT0, 0x35)
ROUND4_16_XX(X2, X3, X4, X5, X6, X7, X0, X1, XT0, 0x36)
ROUND4_16_XX(X1, X2, X3, X4, X5, X6, X7, X0, XT0, 0x37)
ROUND4_16_XX(X0, X1, X2, X3, X4, X5, X6, X7, XT0, 0x38)
ROUND4_16_XX(X7, X0, X1, X2, X3, X4, X5, X6, XT0, 0x39)
ROUND4_16_XX(X6, X7, X0, X1, X2, X3, X4, X5, XT0, 0x3a)
ROUND4_16_XX(X5, X6, X7, X0, X1, X2, X3, X4, XT0, 0x3b)
ROUND4_16_XX(X4, X5, X6, X7, X0, X1, X2, X3, XT0, 0x3c)
ROUND4_16_XX(X3, X4, X5, X6, X7, X0, X1, X2, XT0, 0x3d)
ROUND4_16_XX(X2, X3, X4, X5, X6, X7, X0, X1, XT0, 0x3e)
ROUND4_16_XX(X1, X2, X3, X4, X5, X6, X7, X0, XT0, 0x3f)
// add old digest
MOVQ $_DIGEST_16<>(SB), TBL
VPADDD (0*64)(TBL), X0, X0
VPADDD (1*64)(TBL), X1, X1
VPADDD (2*64)(TBL), X2, X2
VPADDD (3*64)(TBL), X3, X3
VPADDD (4*64)(TBL), X4, X4
VPADDD (5*64)(TBL), X5, X5
VPADDD (6*64)(TBL), X6, X6
VPADDD (7*64)(TBL), X7, X7
// rounds with padding
// save old digest
VMOVDQU X0, (_DIGEST + 0*16)(SP)
VMOVDQU X1, (_DIGEST + 1*16)(SP)
VMOVDQU X2, (_DIGEST + 2*16)(SP)
VMOVDQU X3, (_DIGEST + 3*16)(SP)
VMOVDQU X4, (_DIGEST + 4*16)(SP)
VMOVDQU X5, (_DIGEST + 5*16)(SP)
VMOVDQU X6, (_DIGEST + 6*16)(SP)
VMOVDQU X7, (_DIGEST + 7*16)(SP)
MOVQ $_PADDING_16<>(SB), TBL
ROUND4_00_15_PADD(X0, X1, X2, X3, X4, X5, X6, X7, XT0, 0x00)
ROUND4_00_15_PADD(X7, X0, X1, X2, X3, X4, X5, X6, XT0, 0x01)
ROUND4_00_15_PADD(X6, X7, X0, X1, X2, X3, X4, X5, XT0, 0x02)
ROUND4_00_15_PADD(X5, X6, X7, X0, X1, X2, X3, X4, XT0, 0x03)
ROUND4_00_15_PADD(X4, X5, X6, X7, X0, X1, X2, X3, XT0, 0x04)
ROUND4_00_15_PADD(X3, X4, X5, X6, X7, X0, X1, X2, XT0, 0x05)
ROUND4_00_15_PADD(X2, X3, X4, X5, X6, X7, X0, X1, XT0, 0x06)
ROUND4_00_15_PADD(X1, X2, X3, X4, X5, X6, X7, X0, XT0, 0x07)
ROUND4_00_15_PADD(X0, X1, X2, X3, X4, X5, X6, X7, XT0, 0x08)
ROUND4_00_15_PADD(X7, X0, X1, X2, X3, X4, X5, X6, XT0, 0x09)
ROUND4_00_15_PADD(X6, X7, X0, X1, X2, X3, X4, X5, XT0, 0x0a)
ROUND4_00_15_PADD(X5, X6, X7, X0, X1, X2, X3, X4, XT0, 0x0b)
ROUND4_00_15_PADD(X4, X5, X6, X7, X0, X1, X2, X3, XT0, 0x0c)
ROUND4_00_15_PADD(X3, X4, X5, X6, X7, X0, X1, X2, XT0, 0x0d)
ROUND4_00_15_PADD(X2, X3, X4, X5, X6, X7, X0, X1, XT0, 0x0e)
ROUND4_00_15_PADD(X1, X2, X3, X4, X5, X6, X7, X0, XT0, 0x0f)
ROUND4_00_15_PADD(X0, X1, X2, X3, X4, X5, X6, X7, XT0, 0x10)
ROUND4_00_15_PADD(X7, X0, X1, X2, X3, X4, X5, X6, XT0, 0x11)
ROUND4_00_15_PADD(X6, X7, X0, X1, X2, X3, X4, X5, XT0, 0x12)
ROUND4_00_15_PADD(X5, X6, X7, X0, X1, X2, X3, X4, XT0, 0x13)
ROUND4_00_15_PADD(X4, X5, X6, X7, X0, X1, X2, X3, XT0, 0x14)
ROUND4_00_15_PADD(X3, X4, X5, X6, X7, X0, X1, X2, XT0, 0x15)
ROUND4_00_15_PADD(X2, X3, X4, X5, X6, X7, X0, X1, XT0, 0x16)
ROUND4_00_15_PADD(X1, X2, X3, X4, X5, X6, X7, X0, XT0, 0x17)
ROUND4_00_15_PADD(X0, X1, X2, X3, X4, X5, X6, X7, XT0, 0x18)
ROUND4_00_15_PADD(X7, X0, X1, X2, X3, X4, X5, X6, XT0, 0x19)
ROUND4_00_15_PADD(X6, X7, X0, X1, X2, X3, X4, X5, XT0, 0x1a)
ROUND4_00_15_PADD(X5, X6, X7, X0, X1, X2, X3, X4, XT0, 0x1b)
ROUND4_00_15_PADD(X4, X5, X6, X7, X0, X1, X2, X3, XT0, 0x1c)
ROUND4_00_15_PADD(X3, X4, X5, X6, X7, X0, X1, X2, XT0, 0x1d)
ROUND4_00_15_PADD(X2, X3, X4, X5, X6, X7, X0, X1, XT0, 0x1e)
ROUND4_00_15_PADD(X1, X2, X3, X4, X5, X6, X7, X0, XT0, 0x1f)
ROUND4_00_15_PADD(X0, X1, X2, X3, X4, X5, X6, X7, XT0, 0x20)
ROUND4_00_15_PADD(X7, X0, X1, X2, X3, X4, X5, X6, XT0, 0x21)
ROUND4_00_15_PADD(X6, X7, X0, X1, X2, X3, X4, X5, XT0, 0x22)
ROUND4_00_15_PADD(X5, X6, X7, X0, X1, X2, X3, X4, XT0, 0x23)
ROUND4_00_15_PADD(X4, X5, X6, X7, X0, X1, X2, X3, XT0, 0x24)
ROUND4_00_15_PADD(X3, X4, X5, X6, X7, X0, X1, X2, XT0, 0x25)
ROUND4_00_15_PADD(X2, X3, X4, X5, X6, X7, X0, X1, XT0, 0x26)
ROUND4_00_15_PADD(X1, X2, X3, X4, X5, X6, X7, X0, XT0, 0x27)
ROUND4_00_15_PADD(X0, X1, X2, X3, X4, X5, X6, X7, XT0, 0x28)
ROUND4_00_15_PADD(X7, X0, X1, X2, X3, X4, X5, X6, XT0, 0x29)
ROUND4_00_15_PADD(X6, X7, X0, X1, X2, X3, X4, X5, XT0, 0x2a)
ROUND4_00_15_PADD(X5, X6, X7, X0, X1, X2, X3, X4, XT0, 0x2b)
ROUND4_00_15_PADD(X4, X5, X6, X7, X0, X1, X2, X3, XT0, 0x2c)
ROUND4_00_15_PADD(X3, X4, X5, X6, X7, X0, X1, X2, XT0, 0x2d)
ROUND4_00_15_PADD(X2, X3, X4, X5, X6, X7, X0, X1, XT0, 0x2e)
ROUND4_00_15_PADD(X1, X2, X3, X4, X5, X6, X7, X0, XT0, 0x2f)
ROUND4_00_15_PADD(X0, X1, X2, X3, X4, X5, X6, X7, XT0, 0x30)
ROUND4_00_15_PADD(X7, X0, X1, X2, X3, X4, X5, X6, XT0, 0x31)
ROUND4_00_15_PADD(X6, X7, X0, X1, X2, X3, X4, X5, XT0, 0x32)