By CPX, will AI-Deck use less pins to communicate with Crazyflie in the future?

[twinhorse]

Hi Marcus and bitcraze, your current work on CPX is exciting!

I have been working on AI-Deck for about almost a year. One thing that is not very clear is which UART port will be mainly used for the communication between Crazyflie and AIdeck in the future. Because of the existence of routing, I believe either UART1 or UART2 is enough for the communication between Crazyflie and AIdeck. Which one is more likely to be chosen in the future? Will it be UART2 since you already implemented the communicate to GAP8 via CPX from NINA on ESP32?

To summary a simpler question: the current AI-Deck use a lot pins:RX1, TX1, IO1, IO4,TX2, RX2, to communicate with Crazyflie.
Which pins will still be used in the future and which pins will be free.

[evoggy]

Hi!

Happy to hear that you're excited about CPX 😄

I'm working on some updates for CPX (bitcraze/crazyflie-firmware#1068) and here I've actually disabled the GAP8<>STM32 UART by default (it can of course be re-enabled and used if needed). The issue is that this UART collides with both the LPS and the Lighthouse deck, which might be nice decks to combine with if you want some ground truth. Also, like you said, it's not really used anymore since CPX can do the same thing (although with higher latency). I also think it's nice to free up the GAP8<>STM32 UART so the users can use it for their specific applications if needed.

So, to summarize, the default implementation will use UART2, IO1 and IO4 in the future. But UART1 will be available for users if they want to use it.