diff --git a/makefile b/makefile
index f2eeceb..6b6398b 100644
--- a/makefile
+++ b/makefile
@@ -20,7 +20,7 @@ VERILOG_SOURCES += $(THIS_DIR)/mux4to1.v
 TOPLEVEL = CombinedCUnDP
 
 # MODULE is the basename of the Python test file
-MODULE = test_microprocessor
+MODULE = test.test_microprocessor
 
 # include cocotb's make rules to take care of the simulator setup
 include $(shell cocotb-config --makefiles)/Makefile.sim
\ No newline at end of file
diff --git a/test/__init__.py b/test/__init__.py
new file mode 100644
index 0000000..e69de29
diff --git a/test/__pycache__/__init__.cpython-38.pyc b/test/__pycache__/__init__.cpython-38.pyc
new file mode 100644
index 0000000..7d94f6d
Binary files /dev/null and b/test/__pycache__/__init__.cpython-38.pyc differ
diff --git a/test/__pycache__/test_microprocessor.cpython-38.pyc b/test/__pycache__/test_microprocessor.cpython-38.pyc
new file mode 100644
index 0000000..ad1f6c8
Binary files /dev/null and b/test/__pycache__/test_microprocessor.cpython-38.pyc differ
diff --git a/test_microprocessor.py b/test/test_microprocessor.py
similarity index 100%
rename from test_microprocessor.py
rename to test/test_microprocessor.py