From c050ce91ebb7d34fa0442a2e4555981b06728881 Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Sat, 18 May 2024 17:18:54 -0400 Subject: [PATCH] phy: restore operation at lower (50MHz) sys-clk-freq Following commit 15bc2db, LiteSDCard no longer works properly at the low end of system clock speeds (e.g., 50MHz). Reverting the way `self.ce` and `self.clk` are generated to `comb` instead of `sync`, allows LiteSDCard to operate at the full previous range of system clock speeds. Fixes: 15bc2db Signed-off-by: Gabriel Somlo --- litesdcard/phy.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litesdcard/phy.py b/litesdcard/phy.py index e4cabf5..aac3943 100644 --- a/litesdcard/phy.py +++ b/litesdcard/phy.py @@ -62,14 +62,14 @@ def __init__(self): # SDCard CE Generation. clk_d = Signal() self.sync += clk_d.eq(clk) - self.sync += self.ce.eq(clk & ~clk_d) + self.comb += self.ce.eq(clk & ~clk_d) # Ensure we don't get short pulses on the SDCard Clk. ce_delayed = Signal() ce_latched = Signal() self.sync += If(clk_d, ce_delayed.eq(self.clk_en)) self.comb += If(clk_d, ce_latched.eq(self.clk_en)).Else(ce_latched.eq(ce_delayed)) - self.sync += self.clk.eq(~clk & ce_latched) + self.comb += self.clk.eq(~clk & ce_latched) # SDCard PHY Read ----------------------------------------------------------------------------------