GitHub - elliott614/WISC-microprocessor: Verilog HDL for architecture class. "WISC" mips-based processor. 3 phases. 1: no pipeline. 2: pipeline/forwarding 3: cache

elliott614 / WISC-microprocessor Public

Verilog HDL for architecture class. "WISC" mips-based processor. 3 phases. 1: no pipeline. 2: pipeline/forwarding 3: cache

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
ADDSUB.v		ADDSUB.v
ALU.v		ALU.v
BitCell.v		BitCell.v
D-Flip-Flop.v		D-Flip-Flop.v
Mux2to1_16bit.v		Mux2to1_16bit.v
Mux3to1_16bit.v		Mux3to1_16bit.v
PADDSB.v		PADDSB.v
PC.v		PC.v
PC_control.v		PC_control.v
PC_control.v.bak		PC_control.v.bak
RED.v		RED.v
ReadDecoder_4_16.v		ReadDecoder_4_16.v
Register.v		Register.v
RegisterFile.v		RegisterFile.v
Shifter.v		Shifter.v
WriteDecoder_4_16.v		WriteDecoder_4_16.v
add_16bit_lookahead.v		add_16bit_lookahead.v
add_4bit_lookahead.v		add_4bit_lookahead.v
add_4bit_lookahead_sat.v		add_4bit_lookahead_sat.v
addsub_4bit.v		addsub_4bit.v
control_signals.v		control_signals.v
cpu.v		cpu.v
cpu.v.bak		cpu.v.bak
full_adder_1bit.v		full_adder_1bit.v
full_adder_1bit_GP.v		full_adder_1bit_GP.v
instruction_memory.v		instruction_memory.v
memory.v		memory.v
memory.v.bak		memory.v.bak
project-phase1-testbench.v		project-phase1-testbench.v
project-phase1-testbench.v.bak		project-phase1-testbench.v.bak
sample.img		sample.img
sample.list		sample.list
tADDSUB.v		tADDSUB.v
tPADDSB.v		tPADDSB.v
tRED.v		tRED.v
tShifter.v		tShifter.v
test1.img		test1.img
test1.list		test1.list
test2.img		test2.img
test2.list		test2.list
test3.img		test3.img
test3.list		test3.list