diff --git a/tests/project/designA/file_A1.vhdl b/tests/project/designA/file_A1.vhdl
new file mode 100644
index 00000000..0d7a991d
--- /dev/null
+++ b/tests/project/designA/file_A1.vhdl
@@ -0,0 +1,17 @@
+library IEEE;
+use     IEEE.std_logic_1164.all;
+
+library libCommon;
+use     libCommon.P1.all;
+
+entity A1 is
+	port (
+		signal Clock : in std_logic
+	);
+end entity;
+
+architecture rtl of A1 is
+
+begin
+
+end architecture;
diff --git a/tests/project/designA/file_A2.vhdl b/tests/project/designA/file_A2.vhdl
new file mode 100644
index 00000000..e48cb1c0
--- /dev/null
+++ b/tests/project/designA/file_A2.vhdl
@@ -0,0 +1,20 @@
+library IEEE;
+use     IEEE.std_logic_1164.all;
+
+library libCommon;
+use     libCommon.P2.all;
+
+entity A2 is
+	port (
+		signal Clock : in std_logic
+	);
+end entity;
+
+architecture rtl of A2 is
+
+begin
+  a : entity work.A1
+    port map (
+			Clock => Clock
+    );
+end architecture;
diff --git a/tests/project/designB/file_B1.vhdl b/tests/project/designB/file_B1.vhdl
new file mode 100644
index 00000000..31ae73f7
--- /dev/null
+++ b/tests/project/designB/file_B1.vhdl
@@ -0,0 +1,14 @@
+
+library libraryCommon;
+use     libraryCommon.P2.all;
+
+entity B1 is
+
+end entity;
+
+architecture rtl of B1 is
+
+begin
+
+end architecture;
+
diff --git a/tests/project/lib/file_P1.vhdl b/tests/project/lib/file_P1.vhdl
new file mode 100644
index 00000000..27a2d8d5
--- /dev/null
+++ b/tests/project/lib/file_P1.vhdl
@@ -0,0 +1,8 @@
+
+package P1 is
+
+end package;
+
+package body P1 is
+
+end package body;
diff --git a/tests/project/lib/file_P2.vhdl b/tests/project/lib/file_P2.vhdl
new file mode 100644
index 00000000..b9a22059
--- /dev/null
+++ b/tests/project/lib/file_P2.vhdl
@@ -0,0 +1,10 @@
+
+use work.P1.all;
+
+package P2 is
+
+end package;
+
+package body P2 is
+
+end package body;
diff --git a/tests/unit/GHDL.py b/tests/unit/GHDL.py
index 1e81e6f5..b87393c6 100644
--- a/tests/unit/GHDL.py
+++ b/tests/unit/GHDL.py
@@ -109,45 +109,98 @@ def test_Analyze(self):
 		tool.Terminate()
 		print(tool.ExitCode)
 
-	def test_AnalyzeFile(self):
-		print()
-
+	def _GetAnalyzer(self) -> GHDL:
 		tool = GHDL(binaryDirectoryPath=self._binaryDirectoryPath)
-		tool[tool.CommandAnalyze] = True
 		tool[tool.FlagVHDLStandard] = "08"
 		tool[tool.FlagSynopsys] = True
 		tool[tool.FlagRelaxed] = True
 		tool[tool.FlagExplicit] = True
 		tool[tool.FlagMultiByteComments] = True
+
+		return tool
+
+	def test_AnalyzeFaultyFile(self):
+		print()
+
+		tool = self._GetAnalyzer()
+		tool[tool.CommandAnalyze] = True
 		tool[tool.FlagLibrary] = "lib_Test"
-		tool[tool.OptionPaths] = (Path("example/file_A1.vhdl"), )
+		tool[tool.OptionPaths] = (Path("project/designB/file_B1.vhdl"), )
 
 		executable = self.getExecutablePath("ghdl", self._binaryDirectoryPath)
-		self.assertEqual(f"[\"{executable}\", \"analyze\", \"--std=08\", \"-fsynopsys\", \"-frelaxed\", \"-fexplicit\", \"--work=lib_Test\", \"--mb-comments\", \"example\\file_A1.vhdl\"]", repr(tool))
+		self.assertEqual(f"[\"{executable}\", \"analyze\", \"--std=08\", \"-fsynopsys\", \"-frelaxed\", \"-fexplicit\", \"--work=lib_Test\", \"--mb-comments\", \"project\\designB\\file_B1.vhdl\"]", repr(tool))
 
 		tool.StartProcess()
 		for line in tool.GetLineReader():
 			print(line)
 		tool.Terminate()
-		print(tool.ExitCode)
 
-	def test_DeriveAnalyzer(self):
+		self.assertEqual(1, tool.ExitCode)
+
+	def test_AnalyzeSingleFiles(self):
 		print()
 
-		tool = GHDL(binaryDirectoryPath=self._binaryDirectoryPath)
-		tool[tool.FlagVHDLStandard] = "08"
-		tool[tool.FlagSynopsys] = True
-		tool[tool.FlagRelaxed] = True
-		tool[tool.FlagExplicit] = True
-		tool[tool.FlagMultiByteComments] = True
+		libraryFiles = (
+			Path("project/lib/file_P1.vhdl"),
+			Path("project/lib/file_P2.vhdl"),
+		)
+		designFiles = (
+			Path("project/designA/file_A1.vhdl"),
+			Path("project/designA/file_A2.vhdl"),
+		)
+
+		analyzer = self._GetAnalyzer()
+		for file in libraryFiles:
+			tool = analyzer.GetGHDLAsAnalyzer()
+			tool[tool.FlagLibrary] = "libCommon"
+			tool[tool.OptionPaths] = (file, )
+			tool.StartProcess()
+			for line in tool.GetLineReader():
+				print(line)
+			tool.Terminate()
+
+			self.assertEqual(0, tool.ExitCode)
+
+		for file in designFiles:
+			tool = analyzer.GetGHDLAsAnalyzer()
+			tool[tool.FlagLibrary] = "libDesign"
+			tool[tool.OptionPaths] = (file, )
+			tool.StartProcess()
+			for line in tool.GetLineReader():
+				print(line)
+			tool.Terminate()
+
+			self.assertEqual(0, tool.ExitCode)
+
+	def test_AnalyzeMultipleFiles(self):
+		print()
 
-		derived = tool.GetGHDLAsAnalyzer()
-		derived[derived.FlagLibrary] = "lib_Test"
+		libraryFiles = (
+			Path("project/lib/file_P1.vhdl"),
+			Path("project/lib/file_P2.vhdl"),
+		)
+		designFiles = (
+			Path("project/designA/file_A1.vhdl"),
+			Path("project/designA/file_A2.vhdl"),
+		)
+
+		analyzer = self._GetAnalyzer()
+		tool = analyzer.GetGHDLAsAnalyzer()
+		tool[tool.FlagLibrary] = "libCommon"
+		tool[tool.OptionPaths] = libraryFiles
+		tool.StartProcess()
+		for line in tool.GetLineReader():
+			print(line)
+		tool.Terminate()
 
-		executable = self.getExecutablePath("ghdl", self._binaryDirectoryPath)
-		self.assertEqual(f"[\"{executable}\", \"analyze\", \"--std=08\", \"-fsynopsys\", \"-frelaxed\", \"-fexplicit\", \"--work=lib_Test\", \"--mb-comments\"]", repr(derived))
+		self.assertEqual(0, tool.ExitCode)
 
-		derived.StartProcess()
-		for line in derived.GetLineReader():
+		tool = analyzer.GetGHDLAsAnalyzer()
+		tool[tool.FlagLibrary] = "libDesign"
+		tool[tool.OptionPaths] = designFiles
+		tool.StartProcess()
+		for line in tool.GetLineReader():
 			print(line)
-		print(derived.ExitCode)
+		tool.Terminate()
+
+		self.assertEqual(0, tool.ExitCode)