diff --git a/gateware/cores/pitch_shift_migen.sv b/gateware/cores/pitch_shift_migen.sv new file mode 100644 index 0000000..74c5e61 --- /dev/null +++ b/gateware/cores/pitch_shift_migen.sv @@ -0,0 +1,1918 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : pitch_shift_migen.v +// Device : Unknown +// LiteX sha1 : 2b8f895e +// Date : 2023-10-25 19:53:50 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module pitch_shift_migen #( + W=16 +)( + input wire clk, + input wire jack, + input wire rst, + input wire sample_clk, + input wire signed [15:0] sample_in0, + input wire signed [15:0] sample_in1, + input wire signed [15:0] sample_in2, + input wire signed [15:0] sample_in3, + output reg signed [15:0] sample_out0, + output reg signed [15:0] sample_out1, + output reg signed [15:0] sample_out2, + input wire signed [15:0] sample_out3 +); + + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire sys_clk; +wire sys_rst; +reg testdsp0 = 1'd0; +wire testdsp1; +wire testdsp_endpoint0_first; +wire testdsp_endpoint0_last; +wire signed [31:0] testdsp_endpoint0_payload_a; +wire signed [31:0] testdsp_endpoint0_payload_b; +wire signed [31:0] testdsp_endpoint0_payload_c; +reg signed [15:0] testdsp_endpoint0_payload_sample = 16'd0; +wire testdsp_endpoint0_ready0; +wire testdsp_endpoint0_ready1; +reg testdsp_endpoint0_valid0 = 1'd0; +wire testdsp_endpoint0_valid1; +wire testdsp_endpoint1_first0; +wire testdsp_endpoint1_first1; +wire testdsp_endpoint1_last0; +wire testdsp_endpoint1_last1; +wire signed [31:0] testdsp_endpoint1_payload_delay; +wire signed [31:0] testdsp_endpoint1_payload_z; +reg testdsp_endpoint1_ready0 = 1'd0; +wire testdsp_endpoint1_ready1; +wire testdsp_endpoint1_valid0; +wire testdsp_endpoint1_valid1; +reg testdsp_endpoint2_first = 1'd0; +reg testdsp_endpoint2_last = 1'd0; +wire signed [15:0] testdsp_endpoint2_payload_sample; +wire testdsp_endpoint2_ready; +reg testdsp_endpoint2_valid = 1'd0; +reg [2:0] testdsp_fsm00 = 3'd0; +reg [2:0] testdsp_fsm01 = 3'd0; +reg [2:0] testdsp_fsm10 = 3'd0; +reg [2:0] testdsp_fsm11 = 3'd0; +wire [8:0] testdsp_memory0; +wire [15:0] testdsp_memory1; +wire testdsp_memory2; +wire [15:0] testdsp_memory3; +wire [8:0] testdsp_memory4; +wire [15:0] testdsp_memory5; +reg testdsp_pitchshift00 = 1'd0; +wire signed [31:0] testdsp_pitchshift01; +reg signed [31:0] testdsp_pitchshift010 = 32'd0; +reg signed [31:0] testdsp_pitchshift010_lowernext010 = 32'd0; +reg testdsp_pitchshift010_lowernext011 = 1'd0; +wire [15:0] testdsp_pitchshift02; +reg signed [31:0] testdsp_pitchshift03 = 32'd0; +reg signed [31:0] testdsp_pitchshift03_lowernext0_lowernext00 = 32'd0; +reg testdsp_pitchshift03_lowernext0_lowernext01 = 1'd0; +wire signed [31:0] testdsp_pitchshift04; +reg signed [15:0] testdsp_pitchshift05 = 16'd0; +reg signed [15:0] testdsp_pitchshift05_lowernext00 = 16'd0; +reg testdsp_pitchshift05_lowernext01 = 1'd0; +reg signed [15:0] testdsp_pitchshift06 = 16'd0; +reg signed [15:0] testdsp_pitchshift06_lowernext02 = 16'd0; +reg testdsp_pitchshift06_lowernext03 = 1'd0; +reg signed [31:0] testdsp_pitchshift07 = 32'd0; +reg signed [31:0] testdsp_pitchshift07_lowernext04 = 32'd0; +reg testdsp_pitchshift07_lowernext05 = 1'd0; +reg signed [31:0] testdsp_pitchshift08 = 32'd0; +reg signed [31:0] testdsp_pitchshift08_lowernext06 = 32'd0; +reg testdsp_pitchshift08_lowernext07 = 1'd0; +reg signed [31:0] testdsp_pitchshift09 = 32'd0; +reg signed [31:0] testdsp_pitchshift09_lowernext08 = 32'd0; +reg testdsp_pitchshift09_lowernext09 = 1'd0; +reg signed [15:0] testdsp_pitchshift0_payload_sample = 16'd0; +wire testdsp_pitchshift0_ready; +reg testdsp_pitchshift0_valid = 1'd0; +reg testdsp_pitchshift10 = 1'd0; +wire signed [31:0] testdsp_pitchshift11; +reg signed [31:0] testdsp_pitchshift110 = 32'd0; +reg signed [31:0] testdsp_pitchshift110_lowernext110 = 32'd0; +reg testdsp_pitchshift110_lowernext111 = 1'd0; +wire [15:0] testdsp_pitchshift12; +reg signed [31:0] testdsp_pitchshift13 = 32'd0; +reg signed [31:0] testdsp_pitchshift13_lowernext1_lowernext10 = 32'd0; +reg testdsp_pitchshift13_lowernext1_lowernext11 = 1'd0; +wire signed [31:0] testdsp_pitchshift14; +reg signed [15:0] testdsp_pitchshift15 = 16'd0; +reg signed [15:0] testdsp_pitchshift15_lowernext10 = 16'd0; +reg testdsp_pitchshift15_lowernext11 = 1'd0; +reg signed [15:0] testdsp_pitchshift16 = 16'd0; +reg signed [15:0] testdsp_pitchshift16_lowernext12 = 16'd0; +reg testdsp_pitchshift16_lowernext13 = 1'd0; +reg signed [31:0] testdsp_pitchshift17 = 32'd0; +reg signed [31:0] testdsp_pitchshift17_lowernext14 = 32'd0; +reg testdsp_pitchshift17_lowernext15 = 1'd0; +reg signed [31:0] testdsp_pitchshift18 = 32'd0; +reg signed [31:0] testdsp_pitchshift18_lowernext16 = 32'd0; +reg testdsp_pitchshift18_lowernext17 = 1'd0; +reg signed [31:0] testdsp_pitchshift19 = 32'd0; +reg signed [31:0] testdsp_pitchshift19_lowernext18 = 32'd0; +reg testdsp_pitchshift19_lowernext19 = 1'd0; +reg signed [15:0] testdsp_pitchshift1_payload_sample = 16'd0; +wire testdsp_pitchshift1_ready; +reg testdsp_pitchshift1_valid = 1'd0; +reg [8:0] testdsp_rdpointer = 9'd0; +reg testdsp_rrmux00 = 1'd0; +wire testdsp_rrmux01; +wire testdsp_rrmux0_demultiplexer0; +wire testdsp_rrmux0_demultiplexer0_endpoint0_first; +wire testdsp_rrmux0_demultiplexer0_endpoint0_last; +wire signed [15:0] testdsp_rrmux0_demultiplexer0_endpoint0_payload_sample; +reg testdsp_rrmux0_demultiplexer0_endpoint0_ready = 1'd0; +wire testdsp_rrmux0_demultiplexer0_endpoint0_valid; +reg testdsp_rrmux0_demultiplexer0_endpoint1_first = 1'd0; +reg testdsp_rrmux0_demultiplexer0_endpoint1_last = 1'd0; +reg signed [15:0] testdsp_rrmux0_demultiplexer0_endpoint1_payload_sample = 16'd0; +reg testdsp_rrmux0_demultiplexer0_endpoint1_ready = 1'd0; +reg testdsp_rrmux0_demultiplexer0_endpoint1_valid = 1'd0; +reg testdsp_rrmux0_demultiplexer0_endpoint2_first = 1'd0; +reg testdsp_rrmux0_demultiplexer0_endpoint2_last = 1'd0; +reg signed [15:0] testdsp_rrmux0_demultiplexer0_endpoint2_payload_sample = 16'd0; +reg testdsp_rrmux0_demultiplexer0_endpoint2_ready = 1'd0; +reg testdsp_rrmux0_demultiplexer0_endpoint2_valid = 1'd0; +wire testdsp_rrmux0_multiplexer0; +reg testdsp_rrmux0_multiplexer0_endpoint0_first = 1'd0; +reg testdsp_rrmux0_multiplexer0_endpoint0_last = 1'd0; +reg signed [31:0] testdsp_rrmux0_multiplexer0_endpoint0_payload_delay = 32'd0; +wire testdsp_rrmux0_multiplexer0_endpoint0_ready; +reg testdsp_rrmux0_multiplexer0_endpoint0_valid = 1'd0; +reg testdsp_rrmux0_multiplexer0_endpoint1_first = 1'd0; +reg testdsp_rrmux0_multiplexer0_endpoint1_last = 1'd0; +reg signed [31:0] testdsp_rrmux0_multiplexer0_endpoint1_payload_delay = 32'd0; +reg testdsp_rrmux0_multiplexer0_endpoint1_ready = 1'd0; +reg testdsp_rrmux0_multiplexer0_endpoint1_valid = 1'd0; +reg testdsp_rrmux0_multiplexer0_endpoint2_first = 1'd0; +reg testdsp_rrmux0_multiplexer0_endpoint2_last = 1'd0; +reg signed [31:0] testdsp_rrmux0_multiplexer0_endpoint2_payload_delay = 32'd0; +reg testdsp_rrmux0_multiplexer0_endpoint2_ready = 1'd0; +reg testdsp_rrmux0_multiplexer0_endpoint2_valid = 1'd0; +reg testdsp_rrmux10 = 1'd0; +wire testdsp_rrmux11; +wire testdsp_rrmux1_demultiplexer1; +wire testdsp_rrmux1_demultiplexer1_endpoint3_first; +wire testdsp_rrmux1_demultiplexer1_endpoint3_last; +wire signed [31:0] testdsp_rrmux1_demultiplexer1_endpoint3_payload_z; +reg testdsp_rrmux1_demultiplexer1_endpoint3_ready = 1'd0; +wire testdsp_rrmux1_demultiplexer1_endpoint3_valid; +reg testdsp_rrmux1_demultiplexer1_endpoint4_first = 1'd0; +reg testdsp_rrmux1_demultiplexer1_endpoint4_last = 1'd0; +reg signed [31:0] testdsp_rrmux1_demultiplexer1_endpoint4_payload_z = 32'd0; +reg testdsp_rrmux1_demultiplexer1_endpoint4_ready = 1'd0; +reg testdsp_rrmux1_demultiplexer1_endpoint4_valid = 1'd0; +reg testdsp_rrmux1_demultiplexer1_endpoint5_first = 1'd0; +reg testdsp_rrmux1_demultiplexer1_endpoint5_last = 1'd0; +reg signed [31:0] testdsp_rrmux1_demultiplexer1_endpoint5_payload_z = 32'd0; +reg testdsp_rrmux1_demultiplexer1_endpoint5_ready = 1'd0; +reg testdsp_rrmux1_demultiplexer1_endpoint5_valid = 1'd0; +wire testdsp_rrmux1_multiplexer1; +reg testdsp_rrmux1_multiplexer1_endpoint3_first = 1'd0; +reg testdsp_rrmux1_multiplexer1_endpoint3_last = 1'd0; +reg signed [31:0] testdsp_rrmux1_multiplexer1_endpoint3_payload_a = 32'd0; +reg signed [31:0] testdsp_rrmux1_multiplexer1_endpoint3_payload_b = 32'd0; +reg signed [31:0] testdsp_rrmux1_multiplexer1_endpoint3_payload_c = 32'd0; +wire testdsp_rrmux1_multiplexer1_endpoint3_ready; +reg testdsp_rrmux1_multiplexer1_endpoint3_valid = 1'd0; +reg testdsp_rrmux1_multiplexer1_endpoint4_first = 1'd0; +reg testdsp_rrmux1_multiplexer1_endpoint4_last = 1'd0; +reg signed [31:0] testdsp_rrmux1_multiplexer1_endpoint4_payload_a = 32'd0; +reg signed [31:0] testdsp_rrmux1_multiplexer1_endpoint4_payload_b = 32'd0; +reg signed [31:0] testdsp_rrmux1_multiplexer1_endpoint4_payload_c = 32'd0; +reg testdsp_rrmux1_multiplexer1_endpoint4_ready = 1'd0; +reg testdsp_rrmux1_multiplexer1_endpoint4_valid = 1'd0; +reg testdsp_rrmux1_multiplexer1_endpoint5_first = 1'd0; +reg testdsp_rrmux1_multiplexer1_endpoint5_last = 1'd0; +reg signed [31:0] testdsp_rrmux1_multiplexer1_endpoint5_payload_a = 32'd0; +reg signed [31:0] testdsp_rrmux1_multiplexer1_endpoint5_payload_b = 32'd0; +reg signed [31:0] testdsp_rrmux1_multiplexer1_endpoint5_payload_c = 32'd0; +reg testdsp_rrmux1_multiplexer1_endpoint5_ready = 1'd0; +reg testdsp_rrmux1_multiplexer1_endpoint5_valid = 1'd0; +reg [8:0] testdsp_wrpointer = 9'd0; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign testdsp_pitchshift01 = 32'd4294934528; +assign testdsp_pitchshift02 = 9'd256; +assign testdsp_pitchshift0_ready = 1'd1; +assign testdsp_pitchshift11 = 16'd32768; +assign testdsp_pitchshift12 = 9'd256; +assign testdsp_pitchshift1_ready = 1'd1; +assign testdsp1 = ((sample_clk != testdsp0) & sample_clk); +assign sys_clk = clk; +assign sys_rst = rst; +assign testdsp_endpoint1_valid0 = testdsp_rrmux0_multiplexer0_endpoint0_valid; +assign testdsp_rrmux0_multiplexer0_endpoint0_ready = testdsp_endpoint1_ready0; +assign testdsp_endpoint1_first0 = testdsp_rrmux0_multiplexer0_endpoint0_first; +assign testdsp_endpoint1_last0 = testdsp_rrmux0_multiplexer0_endpoint0_last; +assign testdsp_endpoint1_payload_delay = testdsp_rrmux0_multiplexer0_endpoint0_payload_delay; +assign testdsp_rrmux0_demultiplexer0_endpoint0_valid = testdsp_endpoint2_valid; +assign testdsp_endpoint2_ready = testdsp_rrmux0_demultiplexer0_endpoint0_ready; +assign testdsp_rrmux0_demultiplexer0_endpoint0_first = testdsp_endpoint2_first; +assign testdsp_rrmux0_demultiplexer0_endpoint0_last = testdsp_endpoint2_last; +assign testdsp_rrmux0_demultiplexer0_endpoint0_payload_sample = testdsp_endpoint2_payload_sample; +assign testdsp_rrmux0_multiplexer0 = testdsp_rrmux00; +assign testdsp_rrmux0_demultiplexer0 = testdsp_rrmux01; +assign testdsp_rrmux01 = (testdsp_rrmux00 - 1'd1); +assign testdsp_memory4 = testdsp_rdpointer; +assign testdsp_endpoint2_payload_sample = testdsp_memory5; +always @(*) begin + testdsp_rdpointer <= 9'd0; + if (testdsp_endpoint1_valid0) begin + testdsp_rdpointer <= ($signed({1'd0, testdsp_wrpointer}) - (testdsp_endpoint1_payload_delay >>> 5'd16)); + end +end +assign testdsp_memory0 = testdsp_wrpointer; +assign testdsp_memory2 = testdsp_endpoint0_valid0; +assign testdsp_memory3 = testdsp_endpoint0_payload_sample; +assign testdsp_endpoint0_ready0 = 1'd1; +always @(*) begin + testdsp_rrmux0_multiplexer0_endpoint0_first <= 1'd0; + case (testdsp_rrmux0_multiplexer0) + 1'd0: begin + testdsp_rrmux0_multiplexer0_endpoint0_first <= testdsp_rrmux0_multiplexer0_endpoint1_first; + end + 1'd1: begin + testdsp_rrmux0_multiplexer0_endpoint0_first <= testdsp_rrmux0_multiplexer0_endpoint2_first; + end + endcase +end +always @(*) begin + testdsp_rrmux0_multiplexer0_endpoint0_last <= 1'd0; + case (testdsp_rrmux0_multiplexer0) + 1'd0: begin + testdsp_rrmux0_multiplexer0_endpoint0_last <= testdsp_rrmux0_multiplexer0_endpoint1_last; + end + 1'd1: begin + testdsp_rrmux0_multiplexer0_endpoint0_last <= testdsp_rrmux0_multiplexer0_endpoint2_last; + end + endcase +end +always @(*) begin + testdsp_rrmux0_multiplexer0_endpoint0_payload_delay <= 32'd0; + case (testdsp_rrmux0_multiplexer0) + 1'd0: begin + testdsp_rrmux0_multiplexer0_endpoint0_payload_delay <= testdsp_rrmux0_multiplexer0_endpoint1_payload_delay; + end + 1'd1: begin + testdsp_rrmux0_multiplexer0_endpoint0_payload_delay <= testdsp_rrmux0_multiplexer0_endpoint2_payload_delay; + end + endcase +end +always @(*) begin + testdsp_rrmux0_multiplexer0_endpoint1_ready <= 1'd0; + case (testdsp_rrmux0_multiplexer0) + 1'd0: begin + testdsp_rrmux0_multiplexer0_endpoint1_ready <= testdsp_rrmux0_multiplexer0_endpoint0_ready; + end + 1'd1: begin + end + endcase +end +always @(*) begin + testdsp_rrmux0_multiplexer0_endpoint2_ready <= 1'd0; + case (testdsp_rrmux0_multiplexer0) + 1'd0: begin + end + 1'd1: begin + testdsp_rrmux0_multiplexer0_endpoint2_ready <= testdsp_rrmux0_multiplexer0_endpoint0_ready; + end + endcase +end +always @(*) begin + testdsp_rrmux0_multiplexer0_endpoint0_valid <= 1'd0; + case (testdsp_rrmux0_multiplexer0) + 1'd0: begin + testdsp_rrmux0_multiplexer0_endpoint0_valid <= testdsp_rrmux0_multiplexer0_endpoint1_valid; + end + 1'd1: begin + testdsp_rrmux0_multiplexer0_endpoint0_valid <= testdsp_rrmux0_multiplexer0_endpoint2_valid; + end + endcase +end +always @(*) begin + testdsp_rrmux0_demultiplexer0_endpoint0_ready <= 1'd0; + case (testdsp_rrmux0_demultiplexer0) + 1'd0: begin + testdsp_rrmux0_demultiplexer0_endpoint0_ready <= testdsp_rrmux0_demultiplexer0_endpoint1_ready; + end + 1'd1: begin + testdsp_rrmux0_demultiplexer0_endpoint0_ready <= testdsp_rrmux0_demultiplexer0_endpoint2_ready; + end + endcase +end +always @(*) begin + testdsp_rrmux0_demultiplexer0_endpoint1_valid <= 1'd0; + case (testdsp_rrmux0_demultiplexer0) + 1'd0: begin + testdsp_rrmux0_demultiplexer0_endpoint1_valid <= testdsp_rrmux0_demultiplexer0_endpoint0_valid; + end + 1'd1: begin + end + endcase +end +always @(*) begin + testdsp_rrmux0_demultiplexer0_endpoint1_first <= 1'd0; + case (testdsp_rrmux0_demultiplexer0) + 1'd0: begin + testdsp_rrmux0_demultiplexer0_endpoint1_first <= testdsp_rrmux0_demultiplexer0_endpoint0_first; + end + 1'd1: begin + end + endcase +end +always @(*) begin + testdsp_rrmux0_demultiplexer0_endpoint1_last <= 1'd0; + case (testdsp_rrmux0_demultiplexer0) + 1'd0: begin + testdsp_rrmux0_demultiplexer0_endpoint1_last <= testdsp_rrmux0_demultiplexer0_endpoint0_last; + end + 1'd1: begin + end + endcase +end +always @(*) begin + testdsp_rrmux0_demultiplexer0_endpoint1_payload_sample <= 16'd0; + case (testdsp_rrmux0_demultiplexer0) + 1'd0: begin + testdsp_rrmux0_demultiplexer0_endpoint1_payload_sample <= testdsp_rrmux0_demultiplexer0_endpoint0_payload_sample; + end + 1'd1: begin + end + endcase +end +always @(*) begin + testdsp_rrmux0_demultiplexer0_endpoint2_valid <= 1'd0; + case (testdsp_rrmux0_demultiplexer0) + 1'd0: begin + end + 1'd1: begin + testdsp_rrmux0_demultiplexer0_endpoint2_valid <= testdsp_rrmux0_demultiplexer0_endpoint0_valid; + end + endcase +end +always @(*) begin + testdsp_rrmux0_demultiplexer0_endpoint2_first <= 1'd0; + case (testdsp_rrmux0_demultiplexer0) + 1'd0: begin + end + 1'd1: begin + testdsp_rrmux0_demultiplexer0_endpoint2_first <= testdsp_rrmux0_demultiplexer0_endpoint0_first; + end + endcase +end +always @(*) begin + testdsp_rrmux0_demultiplexer0_endpoint2_last <= 1'd0; + case (testdsp_rrmux0_demultiplexer0) + 1'd0: begin + end + 1'd1: begin + testdsp_rrmux0_demultiplexer0_endpoint2_last <= testdsp_rrmux0_demultiplexer0_endpoint0_last; + end + endcase +end +always @(*) begin + testdsp_rrmux0_demultiplexer0_endpoint2_payload_sample <= 16'd0; + case (testdsp_rrmux0_demultiplexer0) + 1'd0: begin + end + 1'd1: begin + testdsp_rrmux0_demultiplexer0_endpoint2_payload_sample <= testdsp_rrmux0_demultiplexer0_endpoint0_payload_sample; + end + endcase +end +assign testdsp_endpoint0_valid1 = testdsp_rrmux1_multiplexer1_endpoint3_valid; +assign testdsp_rrmux1_multiplexer1_endpoint3_ready = testdsp_endpoint0_ready1; +assign testdsp_endpoint0_first = testdsp_rrmux1_multiplexer1_endpoint3_first; +assign testdsp_endpoint0_last = testdsp_rrmux1_multiplexer1_endpoint3_last; +assign testdsp_endpoint0_payload_a = testdsp_rrmux1_multiplexer1_endpoint3_payload_a; +assign testdsp_endpoint0_payload_b = testdsp_rrmux1_multiplexer1_endpoint3_payload_b; +assign testdsp_endpoint0_payload_c = testdsp_rrmux1_multiplexer1_endpoint3_payload_c; +assign testdsp_rrmux1_demultiplexer1_endpoint3_valid = testdsp_endpoint1_valid1; +assign testdsp_endpoint1_ready1 = testdsp_rrmux1_demultiplexer1_endpoint3_ready; +assign testdsp_rrmux1_demultiplexer1_endpoint3_first = testdsp_endpoint1_first1; +assign testdsp_rrmux1_demultiplexer1_endpoint3_last = testdsp_endpoint1_last1; +assign testdsp_rrmux1_demultiplexer1_endpoint3_payload_z = testdsp_endpoint1_payload_z; +assign testdsp_rrmux1_multiplexer1 = testdsp_rrmux10; +assign testdsp_rrmux1_demultiplexer1 = testdsp_rrmux11; +assign testdsp_rrmux11 = (testdsp_rrmux10 - 1'd0); +assign testdsp_endpoint1_valid1 = testdsp_endpoint0_valid1; +assign testdsp_endpoint1_first1 = testdsp_endpoint0_first; +assign testdsp_endpoint1_last1 = testdsp_endpoint0_last; +assign testdsp_endpoint0_ready1 = testdsp_endpoint1_ready1; +assign testdsp_endpoint1_payload_z = (((testdsp_endpoint0_payload_a * testdsp_endpoint0_payload_b) >>> 5'd16) + testdsp_endpoint0_payload_c); +always @(*) begin + testdsp_rrmux1_multiplexer1_endpoint5_ready <= 1'd0; + case (testdsp_rrmux1_multiplexer1) + 1'd0: begin + end + 1'd1: begin + testdsp_rrmux1_multiplexer1_endpoint5_ready <= testdsp_rrmux1_multiplexer1_endpoint3_ready; + end + endcase +end +always @(*) begin + testdsp_rrmux1_multiplexer1_endpoint3_valid <= 1'd0; + case (testdsp_rrmux1_multiplexer1) + 1'd0: begin + testdsp_rrmux1_multiplexer1_endpoint3_valid <= testdsp_rrmux1_multiplexer1_endpoint4_valid; + end + 1'd1: begin + testdsp_rrmux1_multiplexer1_endpoint3_valid <= testdsp_rrmux1_multiplexer1_endpoint5_valid; + end + endcase +end +always @(*) begin + testdsp_rrmux1_multiplexer1_endpoint3_first <= 1'd0; + case (testdsp_rrmux1_multiplexer1) + 1'd0: begin + testdsp_rrmux1_multiplexer1_endpoint3_first <= testdsp_rrmux1_multiplexer1_endpoint4_first; + end + 1'd1: begin + testdsp_rrmux1_multiplexer1_endpoint3_first <= testdsp_rrmux1_multiplexer1_endpoint5_first; + end + endcase +end +always @(*) begin + testdsp_rrmux1_multiplexer1_endpoint3_last <= 1'd0; + case (testdsp_rrmux1_multiplexer1) + 1'd0: begin + testdsp_rrmux1_multiplexer1_endpoint3_last <= testdsp_rrmux1_multiplexer1_endpoint4_last; + end + 1'd1: begin + testdsp_rrmux1_multiplexer1_endpoint3_last <= testdsp_rrmux1_multiplexer1_endpoint5_last; + end + endcase +end +always @(*) begin + testdsp_rrmux1_multiplexer1_endpoint3_payload_a <= 32'd0; + case (testdsp_rrmux1_multiplexer1) + 1'd0: begin + testdsp_rrmux1_multiplexer1_endpoint3_payload_a <= testdsp_rrmux1_multiplexer1_endpoint4_payload_a; + end + 1'd1: begin + testdsp_rrmux1_multiplexer1_endpoint3_payload_a <= testdsp_rrmux1_multiplexer1_endpoint5_payload_a; + end + endcase +end +always @(*) begin + testdsp_rrmux1_multiplexer1_endpoint3_payload_b <= 32'd0; + case (testdsp_rrmux1_multiplexer1) + 1'd0: begin + testdsp_rrmux1_multiplexer1_endpoint3_payload_b <= testdsp_rrmux1_multiplexer1_endpoint4_payload_b; + end + 1'd1: begin + testdsp_rrmux1_multiplexer1_endpoint3_payload_b <= testdsp_rrmux1_multiplexer1_endpoint5_payload_b; + end + endcase +end +always @(*) begin + testdsp_rrmux1_multiplexer1_endpoint3_payload_c <= 32'd0; + case (testdsp_rrmux1_multiplexer1) + 1'd0: begin + testdsp_rrmux1_multiplexer1_endpoint3_payload_c <= testdsp_rrmux1_multiplexer1_endpoint4_payload_c; + end + 1'd1: begin + testdsp_rrmux1_multiplexer1_endpoint3_payload_c <= testdsp_rrmux1_multiplexer1_endpoint5_payload_c; + end + endcase +end +always @(*) begin + testdsp_rrmux1_multiplexer1_endpoint4_ready <= 1'd0; + case (testdsp_rrmux1_multiplexer1) + 1'd0: begin + testdsp_rrmux1_multiplexer1_endpoint4_ready <= testdsp_rrmux1_multiplexer1_endpoint3_ready; + end + 1'd1: begin + end + endcase +end +always @(*) begin + testdsp_rrmux1_demultiplexer1_endpoint4_first <= 1'd0; + case (testdsp_rrmux1_demultiplexer1) + 1'd0: begin + testdsp_rrmux1_demultiplexer1_endpoint4_first <= testdsp_rrmux1_demultiplexer1_endpoint3_first; + end + 1'd1: begin + end + endcase +end +always @(*) begin + testdsp_rrmux1_demultiplexer1_endpoint4_last <= 1'd0; + case (testdsp_rrmux1_demultiplexer1) + 1'd0: begin + testdsp_rrmux1_demultiplexer1_endpoint4_last <= testdsp_rrmux1_demultiplexer1_endpoint3_last; + end + 1'd1: begin + end + endcase +end +always @(*) begin + testdsp_rrmux1_demultiplexer1_endpoint4_payload_z <= 32'd0; + case (testdsp_rrmux1_demultiplexer1) + 1'd0: begin + testdsp_rrmux1_demultiplexer1_endpoint4_payload_z <= testdsp_rrmux1_demultiplexer1_endpoint3_payload_z; + end + 1'd1: begin + end + endcase +end +always @(*) begin + testdsp_rrmux1_demultiplexer1_endpoint5_valid <= 1'd0; + case (testdsp_rrmux1_demultiplexer1) + 1'd0: begin + end + 1'd1: begin + testdsp_rrmux1_demultiplexer1_endpoint5_valid <= testdsp_rrmux1_demultiplexer1_endpoint3_valid; + end + endcase +end +always @(*) begin + testdsp_rrmux1_demultiplexer1_endpoint5_first <= 1'd0; + case (testdsp_rrmux1_demultiplexer1) + 1'd0: begin + end + 1'd1: begin + testdsp_rrmux1_demultiplexer1_endpoint5_first <= testdsp_rrmux1_demultiplexer1_endpoint3_first; + end + endcase +end +always @(*) begin + testdsp_rrmux1_demultiplexer1_endpoint5_last <= 1'd0; + case (testdsp_rrmux1_demultiplexer1) + 1'd0: begin + end + 1'd1: begin + testdsp_rrmux1_demultiplexer1_endpoint5_last <= testdsp_rrmux1_demultiplexer1_endpoint3_last; + end + endcase +end +always @(*) begin + testdsp_rrmux1_demultiplexer1_endpoint5_payload_z <= 32'd0; + case (testdsp_rrmux1_demultiplexer1) + 1'd0: begin + end + 1'd1: begin + testdsp_rrmux1_demultiplexer1_endpoint5_payload_z <= testdsp_rrmux1_demultiplexer1_endpoint3_payload_z; + end + endcase +end +always @(*) begin + testdsp_rrmux1_demultiplexer1_endpoint3_ready <= 1'd0; + case (testdsp_rrmux1_demultiplexer1) + 1'd0: begin + testdsp_rrmux1_demultiplexer1_endpoint3_ready <= testdsp_rrmux1_demultiplexer1_endpoint4_ready; + end + 1'd1: begin + testdsp_rrmux1_demultiplexer1_endpoint3_ready <= testdsp_rrmux1_demultiplexer1_endpoint5_ready; + end + endcase +end +always @(*) begin + testdsp_rrmux1_demultiplexer1_endpoint4_valid <= 1'd0; + case (testdsp_rrmux1_demultiplexer1) + 1'd0: begin + testdsp_rrmux1_demultiplexer1_endpoint4_valid <= testdsp_rrmux1_demultiplexer1_endpoint3_valid; + end + 1'd1: begin + end + endcase +end +assign testdsp_pitchshift04 = (testdsp_pitchshift03 + $signed({1'd0, (testdsp_pitchshift02 <<< 5'd16)})); +always @(*) begin + testdsp_fsm01 <= 3'd0; + testdsp_fsm01 <= testdsp_fsm00; + case (testdsp_fsm00) + 1'd1: begin + if (testdsp_rrmux0_demultiplexer0_endpoint1_valid) begin + testdsp_fsm01 <= 2'd2; + end + end + 2'd2: begin + if (testdsp_rrmux0_demultiplexer0_endpoint1_valid) begin + testdsp_fsm01 <= 2'd3; + end + end + 2'd3: begin + testdsp_fsm01 <= 3'd4; + end + 3'd4: begin + if (testdsp_rrmux1_demultiplexer1_endpoint4_valid) begin + testdsp_fsm01 <= 3'd5; + end + end + 3'd5: begin + if (testdsp_rrmux1_demultiplexer1_endpoint4_valid) begin + testdsp_fsm01 <= 3'd6; + end + end + 3'd6: begin + if (testdsp_pitchshift0_ready) begin + testdsp_fsm01 <= 1'd0; + end + end + default: begin + if (testdsp_pitchshift00) begin + testdsp_fsm01 <= 1'd1; + end + end + endcase +end +always @(*) begin + testdsp_pitchshift0_valid <= 1'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + testdsp_pitchshift0_valid <= 1'd1; + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift0_payload_sample <= 16'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + testdsp_pitchshift0_payload_sample <= (testdsp_pitchshift09 + testdsp_pitchshift010); + end + default: begin + end + endcase +end +always @(*) begin + testdsp_rrmux1_multiplexer1_endpoint4_valid <= 1'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + testdsp_rrmux1_multiplexer1_endpoint4_valid <= 1'd1; + end + 3'd5: begin + testdsp_rrmux1_multiplexer1_endpoint4_valid <= 1'd1; + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_rrmux1_multiplexer1_endpoint4_payload_a <= 32'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + testdsp_rrmux1_multiplexer1_endpoint4_payload_a <= testdsp_pitchshift05; + end + 3'd5: begin + testdsp_rrmux1_multiplexer1_endpoint4_payload_a <= testdsp_pitchshift06; + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_rrmux1_multiplexer1_endpoint4_payload_b <= 32'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + testdsp_rrmux1_multiplexer1_endpoint4_payload_b <= testdsp_pitchshift07; + end + 3'd5: begin + testdsp_rrmux1_multiplexer1_endpoint4_payload_b <= testdsp_pitchshift08; + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_rrmux1_multiplexer1_endpoint4_payload_c <= 32'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + testdsp_rrmux1_multiplexer1_endpoint4_payload_c <= 1'd0; + end + 3'd5: begin + testdsp_rrmux1_multiplexer1_endpoint4_payload_c <= 1'd0; + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_rrmux0_multiplexer0_endpoint1_valid <= 1'd0; + case (testdsp_fsm00) + 1'd1: begin + testdsp_rrmux0_multiplexer0_endpoint1_valid <= 1'd1; + end + 2'd2: begin + testdsp_rrmux0_multiplexer0_endpoint1_valid <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift03_lowernext0_lowernext00 <= 32'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (testdsp_pitchshift00) begin + if (((testdsp_pitchshift03 + testdsp_pitchshift01) < $signed({1'd0, 1'd0}))) begin + testdsp_pitchshift03_lowernext0_lowernext00 <= ((testdsp_pitchshift03 + testdsp_pitchshift01) + $signed({1'd0, (testdsp_pitchshift02 <<< 5'd16)})); + end else begin + if (((testdsp_pitchshift03 + testdsp_pitchshift01) > $signed({1'd0, (testdsp_pitchshift02 <<< 5'd16)}))) begin + testdsp_pitchshift03_lowernext0_lowernext00 <= ((testdsp_pitchshift03 + testdsp_pitchshift01) - $signed({1'd0, (testdsp_pitchshift02 <<< 5'd16)})); + end else begin + testdsp_pitchshift03_lowernext0_lowernext00 <= (testdsp_pitchshift03 + testdsp_pitchshift01); + end + end + end + end + endcase +end +always @(*) begin + testdsp_pitchshift03_lowernext0_lowernext01 <= 1'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (testdsp_pitchshift00) begin + if (((testdsp_pitchshift03 + testdsp_pitchshift01) < $signed({1'd0, 1'd0}))) begin + testdsp_pitchshift03_lowernext0_lowernext01 <= 1'd1; + end else begin + if (((testdsp_pitchshift03 + testdsp_pitchshift01) > $signed({1'd0, (testdsp_pitchshift02 <<< 5'd16)}))) begin + testdsp_pitchshift03_lowernext0_lowernext01 <= 1'd1; + end else begin + testdsp_pitchshift03_lowernext0_lowernext01 <= 1'd1; + end + end + end + end + endcase +end +always @(*) begin + testdsp_rrmux0_multiplexer0_endpoint1_payload_delay <= 32'd0; + case (testdsp_fsm00) + 1'd1: begin + testdsp_rrmux0_multiplexer0_endpoint1_payload_delay <= testdsp_pitchshift03; + end + 2'd2: begin + testdsp_rrmux0_multiplexer0_endpoint1_payload_delay <= testdsp_pitchshift04; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift05_lowernext00 <= 16'd0; + case (testdsp_fsm00) + 1'd1: begin + if (testdsp_rrmux0_demultiplexer0_endpoint1_valid) begin + testdsp_pitchshift05_lowernext00 <= testdsp_rrmux0_demultiplexer0_endpoint1_payload_sample; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift05_lowernext01 <= 1'd0; + case (testdsp_fsm00) + 1'd1: begin + if (testdsp_rrmux0_demultiplexer0_endpoint1_valid) begin + testdsp_pitchshift05_lowernext01 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift06_lowernext02 <= 16'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + if (testdsp_rrmux0_demultiplexer0_endpoint1_valid) begin + testdsp_pitchshift06_lowernext02 <= testdsp_rrmux0_demultiplexer0_endpoint1_payload_sample; + end + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift06_lowernext03 <= 1'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + if (testdsp_rrmux0_demultiplexer0_endpoint1_valid) begin + testdsp_pitchshift06_lowernext03 <= 1'd1; + end + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift07_lowernext04 <= 32'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (((testdsp_pitchshift03 >>> 5'd16) < $signed({1'd0, 7'd64}))) begin + testdsp_pitchshift07_lowernext04 <= (testdsp_pitchshift03 >>> 3'd6); + end else begin + testdsp_pitchshift07_lowernext04 <= 17'd65536; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_rrmux1_demultiplexer1_endpoint4_ready <= 1'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + testdsp_rrmux1_demultiplexer1_endpoint4_ready <= 1'd1; + end + 3'd5: begin + testdsp_rrmux1_demultiplexer1_endpoint4_ready <= 1'd1; + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift07_lowernext05 <= 1'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (((testdsp_pitchshift03 >>> 5'd16) < $signed({1'd0, 7'd64}))) begin + testdsp_pitchshift07_lowernext05 <= 1'd1; + end else begin + testdsp_pitchshift07_lowernext05 <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift08_lowernext06 <= 32'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (((testdsp_pitchshift03 >>> 5'd16) < $signed({1'd0, 7'd64}))) begin + testdsp_pitchshift08_lowernext06 <= ($signed({1'd0, 17'd65536}) - (testdsp_pitchshift03 >>> 3'd6)); + end else begin + testdsp_pitchshift08_lowernext06 <= 1'd0; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift08_lowernext07 <= 1'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (((testdsp_pitchshift03 >>> 5'd16) < $signed({1'd0, 7'd64}))) begin + testdsp_pitchshift08_lowernext07 <= 1'd1; + end else begin + testdsp_pitchshift08_lowernext07 <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_rrmux0_demultiplexer0_endpoint1_ready <= 1'd0; + case (testdsp_fsm00) + 1'd1: begin + testdsp_rrmux0_demultiplexer0_endpoint1_ready <= 1'd1; + end + 2'd2: begin + testdsp_rrmux0_demultiplexer0_endpoint1_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift09_lowernext08 <= 32'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (testdsp_rrmux1_demultiplexer1_endpoint4_valid) begin + testdsp_pitchshift09_lowernext08 <= testdsp_rrmux1_demultiplexer1_endpoint4_payload_z; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift09_lowernext09 <= 1'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (testdsp_rrmux1_demultiplexer1_endpoint4_valid) begin + testdsp_pitchshift09_lowernext09 <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift010_lowernext010 <= 32'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + if (testdsp_rrmux1_demultiplexer1_endpoint4_valid) begin + testdsp_pitchshift010_lowernext010 <= testdsp_rrmux1_demultiplexer1_endpoint4_payload_z; + end + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift010_lowernext011 <= 1'd0; + case (testdsp_fsm00) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + if (testdsp_rrmux1_demultiplexer1_endpoint4_valid) begin + testdsp_pitchshift010_lowernext011 <= 1'd1; + end + end + 3'd6: begin + end + default: begin + end + endcase +end +assign testdsp_pitchshift14 = (testdsp_pitchshift13 + $signed({1'd0, (testdsp_pitchshift12 <<< 5'd16)})); +always @(*) begin + testdsp_fsm11 <= 3'd0; + testdsp_fsm11 <= testdsp_fsm10; + case (testdsp_fsm10) + 1'd1: begin + if (testdsp_rrmux0_demultiplexer0_endpoint2_valid) begin + testdsp_fsm11 <= 2'd2; + end + end + 2'd2: begin + if (testdsp_rrmux0_demultiplexer0_endpoint2_valid) begin + testdsp_fsm11 <= 2'd3; + end + end + 2'd3: begin + testdsp_fsm11 <= 3'd4; + end + 3'd4: begin + if (testdsp_rrmux1_demultiplexer1_endpoint5_valid) begin + testdsp_fsm11 <= 3'd5; + end + end + 3'd5: begin + if (testdsp_rrmux1_demultiplexer1_endpoint5_valid) begin + testdsp_fsm11 <= 3'd6; + end + end + 3'd6: begin + if (testdsp_pitchshift1_ready) begin + testdsp_fsm11 <= 1'd0; + end + end + default: begin + if (testdsp_pitchshift10) begin + testdsp_fsm11 <= 1'd1; + end + end + endcase +end +always @(*) begin + testdsp_pitchshift13_lowernext1_lowernext10 <= 32'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (testdsp_pitchshift10) begin + if (((testdsp_pitchshift13 + testdsp_pitchshift11) < $signed({1'd0, 1'd0}))) begin + testdsp_pitchshift13_lowernext1_lowernext10 <= ((testdsp_pitchshift13 + testdsp_pitchshift11) + $signed({1'd0, (testdsp_pitchshift12 <<< 5'd16)})); + end else begin + if (((testdsp_pitchshift13 + testdsp_pitchshift11) > $signed({1'd0, (testdsp_pitchshift12 <<< 5'd16)}))) begin + testdsp_pitchshift13_lowernext1_lowernext10 <= ((testdsp_pitchshift13 + testdsp_pitchshift11) - $signed({1'd0, (testdsp_pitchshift12 <<< 5'd16)})); + end else begin + testdsp_pitchshift13_lowernext1_lowernext10 <= (testdsp_pitchshift13 + testdsp_pitchshift11); + end + end + end + end + endcase +end +always @(*) begin + testdsp_pitchshift13_lowernext1_lowernext11 <= 1'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + if (testdsp_pitchshift10) begin + if (((testdsp_pitchshift13 + testdsp_pitchshift11) < $signed({1'd0, 1'd0}))) begin + testdsp_pitchshift13_lowernext1_lowernext11 <= 1'd1; + end else begin + if (((testdsp_pitchshift13 + testdsp_pitchshift11) > $signed({1'd0, (testdsp_pitchshift12 <<< 5'd16)}))) begin + testdsp_pitchshift13_lowernext1_lowernext11 <= 1'd1; + end else begin + testdsp_pitchshift13_lowernext1_lowernext11 <= 1'd1; + end + end + end + end + endcase +end +always @(*) begin + testdsp_pitchshift15_lowernext10 <= 16'd0; + case (testdsp_fsm10) + 1'd1: begin + if (testdsp_rrmux0_demultiplexer0_endpoint2_valid) begin + testdsp_pitchshift15_lowernext10 <= testdsp_rrmux0_demultiplexer0_endpoint2_payload_sample; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift15_lowernext11 <= 1'd0; + case (testdsp_fsm10) + 1'd1: begin + if (testdsp_rrmux0_demultiplexer0_endpoint2_valid) begin + testdsp_pitchshift15_lowernext11 <= 1'd1; + end + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift16_lowernext12 <= 16'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + if (testdsp_rrmux0_demultiplexer0_endpoint2_valid) begin + testdsp_pitchshift16_lowernext12 <= testdsp_rrmux0_demultiplexer0_endpoint2_payload_sample; + end + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift16_lowernext13 <= 1'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + if (testdsp_rrmux0_demultiplexer0_endpoint2_valid) begin + testdsp_pitchshift16_lowernext13 <= 1'd1; + end + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift17_lowernext14 <= 32'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (((testdsp_pitchshift13 >>> 5'd16) < $signed({1'd0, 7'd64}))) begin + testdsp_pitchshift17_lowernext14 <= (testdsp_pitchshift13 >>> 3'd6); + end else begin + testdsp_pitchshift17_lowernext14 <= 17'd65536; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift17_lowernext15 <= 1'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (((testdsp_pitchshift13 >>> 5'd16) < $signed({1'd0, 7'd64}))) begin + testdsp_pitchshift17_lowernext15 <= 1'd1; + end else begin + testdsp_pitchshift17_lowernext15 <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift18_lowernext16 <= 32'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (((testdsp_pitchshift13 >>> 5'd16) < $signed({1'd0, 7'd64}))) begin + testdsp_pitchshift18_lowernext16 <= ($signed({1'd0, 17'd65536}) - (testdsp_pitchshift13 >>> 3'd6)); + end else begin + testdsp_pitchshift18_lowernext16 <= 1'd0; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift18_lowernext17 <= 1'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + if (((testdsp_pitchshift13 >>> 5'd16) < $signed({1'd0, 7'd64}))) begin + testdsp_pitchshift18_lowernext17 <= 1'd1; + end else begin + testdsp_pitchshift18_lowernext17 <= 1'd1; + end + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift19_lowernext18 <= 32'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (testdsp_rrmux1_demultiplexer1_endpoint5_valid) begin + testdsp_pitchshift19_lowernext18 <= testdsp_rrmux1_demultiplexer1_endpoint5_payload_z; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift19_lowernext19 <= 1'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + if (testdsp_rrmux1_demultiplexer1_endpoint5_valid) begin + testdsp_pitchshift19_lowernext19 <= 1'd1; + end + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift110_lowernext110 <= 32'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + if (testdsp_rrmux1_demultiplexer1_endpoint5_valid) begin + testdsp_pitchshift110_lowernext110 <= testdsp_rrmux1_demultiplexer1_endpoint5_payload_z; + end + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift110_lowernext111 <= 1'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + if (testdsp_rrmux1_demultiplexer1_endpoint5_valid) begin + testdsp_pitchshift110_lowernext111 <= 1'd1; + end + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_rrmux1_multiplexer1_endpoint5_valid <= 1'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + testdsp_rrmux1_multiplexer1_endpoint5_valid <= 1'd1; + end + 3'd5: begin + testdsp_rrmux1_multiplexer1_endpoint5_valid <= 1'd1; + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_rrmux1_multiplexer1_endpoint5_payload_a <= 32'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + testdsp_rrmux1_multiplexer1_endpoint5_payload_a <= testdsp_pitchshift15; + end + 3'd5: begin + testdsp_rrmux1_multiplexer1_endpoint5_payload_a <= testdsp_pitchshift16; + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift1_valid <= 1'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + testdsp_pitchshift1_valid <= 1'd1; + end + default: begin + end + endcase +end +always @(*) begin + testdsp_rrmux1_multiplexer1_endpoint5_payload_b <= 32'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + testdsp_rrmux1_multiplexer1_endpoint5_payload_b <= testdsp_pitchshift17; + end + 3'd5: begin + testdsp_rrmux1_multiplexer1_endpoint5_payload_b <= testdsp_pitchshift18; + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_rrmux1_multiplexer1_endpoint5_payload_c <= 32'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + testdsp_rrmux1_multiplexer1_endpoint5_payload_c <= 1'd0; + end + 3'd5: begin + testdsp_rrmux1_multiplexer1_endpoint5_payload_c <= 1'd0; + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_rrmux0_multiplexer0_endpoint2_valid <= 1'd0; + case (testdsp_fsm10) + 1'd1: begin + testdsp_rrmux0_multiplexer0_endpoint2_valid <= 1'd1; + end + 2'd2: begin + testdsp_rrmux0_multiplexer0_endpoint2_valid <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_pitchshift1_payload_sample <= 16'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + testdsp_pitchshift1_payload_sample <= (testdsp_pitchshift19 + testdsp_pitchshift110); + end + default: begin + end + endcase +end +always @(*) begin + testdsp_rrmux0_multiplexer0_endpoint2_payload_delay <= 32'd0; + case (testdsp_fsm10) + 1'd1: begin + testdsp_rrmux0_multiplexer0_endpoint2_payload_delay <= testdsp_pitchshift13; + end + 2'd2: begin + testdsp_rrmux0_multiplexer0_endpoint2_payload_delay <= testdsp_pitchshift14; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_rrmux1_demultiplexer1_endpoint5_ready <= 1'd0; + case (testdsp_fsm10) + 1'd1: begin + end + 2'd2: begin + end + 2'd3: begin + end + 3'd4: begin + testdsp_rrmux1_demultiplexer1_endpoint5_ready <= 1'd1; + end + 3'd5: begin + testdsp_rrmux1_demultiplexer1_endpoint5_ready <= 1'd1; + end + 3'd6: begin + end + default: begin + end + endcase +end +always @(*) begin + testdsp_rrmux0_demultiplexer0_endpoint2_ready <= 1'd0; + case (testdsp_fsm10) + 1'd1: begin + testdsp_rrmux0_demultiplexer0_endpoint2_ready <= 1'd1; + end + 2'd2: begin + testdsp_rrmux0_demultiplexer0_endpoint2_ready <= 1'd1; + end + 2'd3: begin + end + 3'd4: begin + end + 3'd5: begin + end + 3'd6: begin + end + default: begin + end + endcase +end + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge sys_clk) begin + if (testdsp_pitchshift0_valid) begin + sample_out0 <= sample_in0; + sample_out1 <= testdsp_pitchshift0_payload_sample; + end + if (testdsp_pitchshift1_valid) begin + sample_out2 <= testdsp_pitchshift1_payload_sample; + end + if (testdsp1) begin + testdsp_endpoint0_payload_sample <= sample_in0; + testdsp_endpoint0_valid0 <= 1'd1; + testdsp_pitchshift00 <= 1'd1; + testdsp_pitchshift10 <= 1'd1; + end else begin + testdsp_endpoint0_valid0 <= 1'd0; + testdsp_pitchshift00 <= 1'd0; + testdsp_pitchshift10 <= 1'd0; + end + testdsp0 <= sample_clk; + if ((testdsp_rrmux00 != 1'd1)) begin + testdsp_rrmux00 <= (testdsp_rrmux00 + 1'd1); + end else begin + testdsp_rrmux00 <= 1'd0; + end + testdsp_endpoint2_valid <= testdsp_endpoint1_valid0; + testdsp_endpoint2_first <= testdsp_endpoint1_first0; + testdsp_endpoint2_last <= testdsp_endpoint1_last0; + testdsp_endpoint1_ready0 <= testdsp_endpoint2_ready; + if (testdsp_memory2) begin + if ((testdsp_wrpointer != 9'd511)) begin + testdsp_wrpointer <= (testdsp_wrpointer + 1'd1); + end else begin + testdsp_wrpointer <= 1'd0; + end + end + if ((testdsp_rrmux10 != 1'd1)) begin + testdsp_rrmux10 <= (testdsp_rrmux10 + 1'd1); + end else begin + testdsp_rrmux10 <= 1'd0; + end + testdsp_fsm00 <= testdsp_fsm01; + if (testdsp_pitchshift03_lowernext0_lowernext01) begin + testdsp_pitchshift03 <= testdsp_pitchshift03_lowernext0_lowernext00; + end + if (testdsp_pitchshift05_lowernext01) begin + testdsp_pitchshift05 <= testdsp_pitchshift05_lowernext00; + end + if (testdsp_pitchshift06_lowernext03) begin + testdsp_pitchshift06 <= testdsp_pitchshift06_lowernext02; + end + if (testdsp_pitchshift07_lowernext05) begin + testdsp_pitchshift07 <= testdsp_pitchshift07_lowernext04; + end + if (testdsp_pitchshift08_lowernext07) begin + testdsp_pitchshift08 <= testdsp_pitchshift08_lowernext06; + end + if (testdsp_pitchshift09_lowernext09) begin + testdsp_pitchshift09 <= testdsp_pitchshift09_lowernext08; + end + if (testdsp_pitchshift010_lowernext011) begin + testdsp_pitchshift010 <= testdsp_pitchshift010_lowernext010; + end + testdsp_fsm10 <= testdsp_fsm11; + if (testdsp_pitchshift13_lowernext1_lowernext11) begin + testdsp_pitchshift13 <= testdsp_pitchshift13_lowernext1_lowernext10; + end + if (testdsp_pitchshift15_lowernext11) begin + testdsp_pitchshift15 <= testdsp_pitchshift15_lowernext10; + end + if (testdsp_pitchshift16_lowernext13) begin + testdsp_pitchshift16 <= testdsp_pitchshift16_lowernext12; + end + if (testdsp_pitchshift17_lowernext15) begin + testdsp_pitchshift17 <= testdsp_pitchshift17_lowernext14; + end + if (testdsp_pitchshift18_lowernext17) begin + testdsp_pitchshift18 <= testdsp_pitchshift18_lowernext16; + end + if (testdsp_pitchshift19_lowernext19) begin + testdsp_pitchshift19 <= testdsp_pitchshift19_lowernext18; + end + if (testdsp_pitchshift110_lowernext111) begin + testdsp_pitchshift110 <= testdsp_pitchshift110_lowernext110; + end + if (sys_rst) begin + testdsp_endpoint0_valid0 <= 1'd0; + testdsp_endpoint0_payload_sample <= 16'd0; + testdsp_endpoint1_ready0 <= 1'd0; + testdsp_endpoint2_valid <= 1'd0; + testdsp_wrpointer <= 9'd0; + testdsp_rrmux00 <= 1'd0; + testdsp_rrmux10 <= 1'd0; + testdsp_pitchshift00 <= 1'd0; + testdsp_pitchshift03 <= 32'd0; + testdsp_pitchshift05 <= 16'd0; + testdsp_pitchshift06 <= 16'd0; + testdsp_pitchshift07 <= 32'd0; + testdsp_pitchshift08 <= 32'd0; + testdsp_pitchshift09 <= 32'd0; + testdsp_pitchshift010 <= 32'd0; + testdsp_pitchshift10 <= 1'd0; + testdsp_pitchshift13 <= 32'd0; + testdsp_pitchshift15 <= 16'd0; + testdsp_pitchshift16 <= 16'd0; + testdsp_pitchshift17 <= 32'd0; + testdsp_pitchshift18 <= 32'd0; + testdsp_pitchshift19 <= 32'd0; + testdsp_pitchshift110 <= 32'd0; + sample_out0 <= 16'd0; + sample_out1 <= 16'd0; + sample_out2 <= 16'd0; + testdsp0 <= 1'd0; + testdsp_fsm00 <= 3'd0; + testdsp_fsm10 <= 3'd0; + end +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Memory mem: 512-words x 16-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 16 +// Port 1 | Read: Sync | Write: ---- | +reg [15:0] mem[0:511]; +reg [15:0] mem_dat0; +reg [15:0] mem_dat1; +always @(posedge sys_clk) begin + if (testdsp_memory2) + mem[testdsp_memory0] <= testdsp_memory3; + mem_dat0 <= mem[testdsp_memory0]; +end +always @(posedge sys_clk) begin + mem_dat1 <= mem[testdsp_memory4]; +end +assign testdsp_memory1 = mem_dat0; +assign testdsp_memory5 = mem_dat1; + + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2023-10-25 19:53:50. +//------------------------------------------------------------------------------ + diff --git a/gateware/sim/integration/Makefile b/gateware/sim/integration/Makefile index a1f2751..e4e65de 100644 --- a/gateware/sim/integration/Makefile +++ b/gateware/sim/integration/Makefile @@ -10,9 +10,9 @@ VERILOG_SOURCES = ../../top.sv \ ../../external/no2misc/rtl/i2c_master.v \ ../../cal/debug_uart.sv \ ../../external/no2misc/rtl/uart_tx.v \ - ../../cores/mirror.sv + ../../cores/pitch_shift_migen.sv MODULE = tb_integration -COMPILE_ARGS += -DSELECTED_DSP_CORE=mirror +COMPILE_ARGS += -DSELECTED_DSP_CORE=pitch_shift_migen -pfileline=1 include $(shell cocotb-config --makefiles)/Makefile.sim diff --git a/gateware/sim/integration/tb_integration.py b/gateware/sim/integration/tb_integration.py index 24f74df..9ce2f8e 100644 --- a/gateware/sim/integration/tb_integration.py +++ b/gateware/sim/integration/tb_integration.py @@ -40,13 +40,13 @@ async def test_integration_00(dut): dut = dut.eurorack_pmod1.ak4619_instance - N = 20 + N = 1000 await FallingEdge(dut.lrck) for i in range(N): - v = signed_to_twos_comp(int(16000*math.sin((2*math.pi*i)/N))) + v = signed_to_twos_comp(int(16000*math.sin((2*math.pi*i)/(N/10)))) await clock_out_word(dut, v << 16) await clock_out_word(dut, v << 16)