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x393_parallel.timing_summary_impl
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x393_parallel.timing_summary_impl
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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Thu Apr 4 09:37:26 2019
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_timing_summary -file vivado_build/x393.timing_summary_impl
| Design : x393
| Device : 7z030-fbg484
| Speed File : -1 PRODUCTION 1.11 2014-09-11
------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : false
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops
1. checking no_clock
--------------------
There are 16 register/latch pins with no clock driven by root clock pin: DQSL (HIGH)
There are 16 register/latch pins with no clock driven by root clock pin: DQSU (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: ffclk1p (HIGH)
There is 1 register/latch pin with no clock driven by root clock pin: memclk (HIGH)
2. checking constant_clock
--------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock
-----------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints
--------------------------------------------
There are 20 pins that are not constrained for maximum delay. (HIGH)
There are 0 pins that are not constrained for maximum delay due to constant clock.
5. checking no_input_delay
--------------------------
There are 98 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay
---------------------------
There are 87 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock
--------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks
----------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops
-----------------
There are 0 combinational loops in the design.
10. checking partial_input_delay
--------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay
---------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops
------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
0.128 0.000 0 149853 0.026 0.000 0 149853 0.264 0.000 0 60954
All user specified timing constraints are met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
axi_aclk {0.000 10.000} 20.000 50.000
axihp_clk {0.000 3.333} 6.667 150.000
clk_fb {0.000 10.000} 20.000 50.000
ddr3_clk {0.000 1.250} 2.500 400.000
ddr3_clk_div {0.000 2.500} 5.000 200.000
ddr3_clk_ref {0.000 2.500} 5.000 200.000
ddr3_mclk {1.250 3.750} 5.000 200.000
ddr3_sdclk {0.000 1.250} 2.500 400.000
multi_clkfb {0.000 10.000} 20.000 50.000
sclk {0.000 5.000} 10.000 100.000
xclk {0.000 2.083} 4.167 240.000
ffclk0 {0.000 20.833} 41.667 24.000
clkfb {0.000 20.833} 41.667 24.000
pclk {0.000 5.208} 10.417 95.999
clk_fb_1 {0.000 5.208} 10.417 95.999
clk_fb_2 {0.000 5.208} 10.417 95.999
clk_fb_3 {0.000 5.208} 10.417 95.999
clk_fb_4 {0.000 5.208} 10.417 95.999
iclk0 {0.000 5.208} 10.417 95.999
iclk1 {0.000 5.208} 10.417 95.999
iclk2 {0.000 5.208} 10.417 95.999
iclk2x0 {0.000 2.604} 5.208 191.998
iclk2x1 {0.000 2.604} 5.208 191.998
iclk2x2 {0.000 2.604} 5.208 191.998
iclk2x3 {0.000 2.604} 5.208 191.998
iclk3 {0.000 5.208} 10.417 95.999
gtrefclk {0.000 3.333} 6.666 150.015
rx_clk {0.000 3.333} 6.666 150.015
txoutclk {0.000 3.333} 6.666 150.015
usrclk2 {0.000 6.666} 13.333 75.002
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
axi_aclk 14.251 0.000 0 2685 0.044 0.000 0 2685 7.000 0.000 0 737
axihp_clk 0.593 0.000 0 10211 0.038 0.000 0 10211 0.267 0.000 0 3863
clk_fb 18.751 0.000 0 2
ddr3_clk 0.279 0.000 0 45
ddr3_clk_div 0.309 0.000 0 2158 0.136 0.000 0 2158 1.389 0.000 0 755
ddr3_clk_ref 0.264 0.000 0 5
ddr3_mclk 0.179 0.000 0 82462 0.026 0.000 0 82462 1.389 0.000 0 33208
ddr3_sdclk 1.092 0.000 0 3
multi_clkfb 18.751 0.000 0 2
sclk 4.219 0.000 0 2742 0.044 0.000 0 2742 4.090 0.000 0 1349
xclk 0.165 0.000 0 33063 0.046 0.000 0 33063 0.875 0.000 0 13458
ffclk0 40.567 0.000 0 1 0.414 0.000 0 1 10.833 0.000 0 2
clkfb 10.966 0.000 0 2
pclk 0.597 0.000 0 8201 0.034 0.000 0 8201 2.208 0.000 0 4171
clk_fb_1 9.168 0.000 0 2
clk_fb_2 9.168 0.000 0 2
clk_fb_3 9.168 0.000 0 2
clk_fb_4 9.168 0.000 0 2
iclk0 7.036 0.000 0 425 0.108 0.000 0 425 4.298 0.000 0 177
iclk1 7.024 0.000 0 425 0.095 0.000 0 425 4.298 0.000 0 177
iclk2 7.358 0.000 0 425 0.118 0.000 0 425 4.298 0.000 0 177
iclk2x0 3.801 0.000 0 30
iclk2x1 3.608 0.000 0 30
iclk2x2 3.801 0.000 0 30
iclk2x3 3.608 0.000 0 30
iclk3 4.563 0.000 0 425 0.126 0.000 0 425 4.298 0.000 0 177
gtrefclk 3.890 0.000 0 45 0.209 0.000 0 45 2.553 0.000 0 25
rx_clk 0.543 0.000 0 917 0.068 0.000 0 917 2.423 0.000 0 329
txoutclk 0.708 0.000 0 232 0.139 0.000 0 232 2.666 0.000 0 138
usrclk2 4.605 0.000 0 4577 0.034 0.000 0 4577 5.756 0.000 0 2024
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
ddr3_clk_div ddr3_clk 0.287 0.000 0 23 0.239 0.000 0 23
ddr3_mclk ddr3_clk_div 0.128 0.000 0 146 1.389 0.000 0 146
ddr3_clk_div ddr3_mclk 2.884 0.000 0 76 0.426 0.000 0 76
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
**async_default** axihp_clk axihp_clk 0.989 0.000 0 23 0.471 0.000 0 23
**async_default** ddr3_mclk ddr3_mclk 0.519 0.000 0 453 0.298 0.000 0 453
**async_default** iclk0 iclk0 7.715 0.000 0 6 0.515 0.000 0 6
**async_default** iclk1 iclk1 7.622 0.000 0 6 0.682 0.000 0 6
**async_default** iclk2 iclk2 7.708 0.000 0 6 0.322 0.000 0 6
**async_default** iclk3 iclk3 5.819 0.000 0 6 0.358 0.000 0 6
**async_default** pclk pclk 5.255 0.000 0 20 0.225 0.000 0 20
**async_default** sclk sclk 5.985 0.000 0 16 0.359 0.000 0 16
**async_default** usrclk2 usrclk2 6.232 0.000 0 7 0.942 0.000 0 7
**async_default** xclk xclk 0.625 0.000 0 72 0.412 0.000 0 72
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
From Clock: axi_aclk
To Clock: axi_aclk
Setup : 0 Failing Endpoints, Worst Slack 14.251ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.044ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 7.000ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 14.251ns (required time - arrival time)
Source: mcntrl393_i/chn3rd_buf_i/ram_512x64w_1kx32r_i/ram_i/RAMB36E1_i/CLKARDCLK
(rising edge-triggered cell RAMB36E1 clocked by axi_aclk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: ps7_i/MAXIGP0RDATA[6]
(rising edge-triggered cell PS7 clocked by axi_aclk {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: axi_aclk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 20.000ns (axi_aclk rise@20.000ns - axi_aclk rise@0.000ns)
Data Path Delay: 5.029ns (logic 0.907ns (18.034%) route 4.122ns (81.966%))
Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1)
Clock Path Skew: -0.135ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 1.336ns = ( 21.336 - 20.000 )
Source Clock Delay (SCD): 1.481ns
Clock Pessimism Removal (CPR): 0.010ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axi_aclk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.481 1.481 mcntrl393_i/chn3rd_buf_i/ram_512x64w_1kx32r_i/ram_i/axi_clk
RAMB36_X5Y27 RAMB36E1 r mcntrl393_i/chn3rd_buf_i/ram_512x64w_1kx32r_i/ram_i/RAMB36E1_i/CLKARDCLK
------------------------------------------------------------------- -------------------
RAMB36_X5Y27 RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[6])
0.748 2.229 r mcntrl393_i/chn3rd_buf_i/ram_512x64w_1kx32r_i/ram_i/RAMB36E1_i/DOADO[6]
net (fo=1, routed) 1.183 3.412 cmd_readback_i/lopt_29
SLICE_X70Y135 LUT4 (Prop_lut4_I2_O) 0.053 3.465 r cmd_readback_i/xlnx_opt_LUT_ps7_i_i_55/O
net (fo=1, routed) 0.724 4.189 cmd_readback_i/xlnx_opt_MAXIGP0RDATA[6]_1
SLICE_X70Y140 LUT5 (Prop_lut5_I4_O) 0.053 4.242 r cmd_readback_i/xlnx_opt_LUT_ps7_i_i_55_1/O
net (fo=1, routed) 0.929 5.171 cmd_readback_i/xlnx_opt_MAXIGP0RDATA[6]
SLICE_X65Y145 LUT6 (Prop_lut6_I5_O) 0.053 5.224 r cmd_readback_i/xlnx_opt_LUT_ps7_i_i_55_2/O
net (fo=1, routed) 1.286 6.510 axird_rdata[6]
PS7_X0Y0 PS7 r ps7_i/MAXIGP0RDATA[6]
------------------------------------------------------------------- -------------------
(clock axi_aclk rise edge)
20.000 20.000 r
BUFGCTRL_X0Y23 BUFG 0.000 20.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.336 21.336 axi_aclk
PS7_X0Y0 PS7 r ps7_i/MAXIGP0ACLK
clock pessimism 0.010 21.346
clock uncertainty -0.035 21.311
PS7_X0Y0 PS7 (Setup_ps7_MAXIGP0ACLK_MAXIGP0RDATA[6])
-0.550 20.761 ps7_i
-------------------------------------------------------------------
required time 20.761
arrival time -6.510
-------------------------------------------------------------------
slack 14.251
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.044ns (arrival time - required time)
Source: axibram_read_i/raddr_i/inreg_reg[22]/C
(rising edge-triggered cell FDRE clocked by axi_aclk {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: axibram_read_i/raddr_i/ram_reg_0_15_18_23/RAMC/I
(rising edge-triggered cell RAMD32 clocked by axi_aclk {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: axi_aclk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (axi_aclk rise@0.000ns - axi_aclk rise@0.000ns)
Data Path Delay: 0.146ns (logic 0.091ns (62.374%) route 0.055ns (37.626%))
Logic Levels: 0
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 0.755ns
Source Clock Delay (SCD): 0.549ns
Clock Pessimism Removal (CPR): 0.195ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axi_aclk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.549 0.549 axibram_read_i/raddr_i/axi_clk
SLICE_X27Y140 FDRE r axibram_read_i/raddr_i/inreg_reg[22]/C
------------------------------------------------------------------- -------------------
SLICE_X27Y140 FDRE (Prop_fdre_C_Q) 0.091 0.640 r axibram_read_i/raddr_i/inreg_reg[22]/Q
net (fo=1, routed) 0.055 0.695 axibram_read_i/raddr_i/ram_reg_0_15_18_23/DIC0
SLICE_X26Y140 RAMD32 r axibram_read_i/raddr_i/ram_reg_0_15_18_23/RAMC/I
------------------------------------------------------------------- -------------------
(clock axi_aclk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.755 0.755 axibram_read_i/raddr_i/ram_reg_0_15_18_23/WCLK
SLICE_X26Y140 RAMD32 r axibram_read_i/raddr_i/ram_reg_0_15_18_23/RAMC/CLK
clock pessimism -0.195 0.560
SLICE_X26Y140 RAMD32 (Hold_ramd32_CLK_I)
0.091 0.651 axibram_read_i/raddr_i/ram_reg_0_15_18_23/RAMC
-------------------------------------------------------------------
required time -0.651
arrival time 0.695
-------------------------------------------------------------------
slack 0.044
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: axi_aclk
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { clocks393_i/bufg_axi_aclk_i/O }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.183 20.000 17.817 RAMB36_X3Y29 cmd_readback_i/ram_reg_0/CLKBWRCLK
Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 20.000 32.633 PLLE2_ADV_X1Y3 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X1Y3 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 3.000 10.000 7.000 PLLE2_ADV_X1Y3 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKIN1
---------------------------------------------------------------------------------------------------
From Clock: axihp_clk
To Clock: axihp_clk
Setup : 0 Failing Endpoints, Worst Slack 0.593ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.038ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 0.267ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.593ns (required time - arrival time)
Source: sata_top/ahci_top_i/axi_ahci_regs_i/drp_read_data_reg[1]/C
(rising edge-triggered cell FDRE clocked by axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns})
Destination: sata_top/ahci_top_i/axi_ahci_regs_i/bram_rdata_r_reg[1]/D
(rising edge-triggered cell FDRE clocked by axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns})
Path Group: axihp_clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 6.667ns (axihp_clk rise@6.667ns - axihp_clk rise@0.000ns)
Data Path Delay: 5.652ns (logic 0.322ns (5.697%) route 5.330ns (94.303%))
Logic Levels: 1 (LUT5=1)
Clock Path Skew: -0.384ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.815ns = ( 11.482 - 6.667 )
Source Clock Delay (SCD): 5.516ns
Clock Pessimism Removal (CPR): 0.317ns
Clock Uncertainty: 0.071ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.124ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axihp_clk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.784 1.784 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.088 1.872 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.868 3.740 clocks393_i/hclk_i/hclk_pre
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.120 3.860 r clocks393_i/hclk_i/clk1x_i/O
net (fo=3868, routed) 1.656 5.516 sata_top/ahci_top_i/axi_ahci_regs_i/hclk
SLICE_X111Y3 FDRE r sata_top/ahci_top_i/axi_ahci_regs_i/drp_read_data_reg[1]/C
------------------------------------------------------------------- -------------------
SLICE_X111Y3 FDRE (Prop_fdre_C_Q) 0.269 5.785 r sata_top/ahci_top_i/axi_ahci_regs_i/drp_read_data_reg[1]/Q
net (fo=1, routed) 5.330 11.115 sata_top/ahci_top_i/axi_ahci_regs_i/ahci_regs_i/drp_read_data_reg[15][1]
SLICE_X37Y147 LUT5 (Prop_lut5_I0_O) 0.053 11.168 r sata_top/ahci_top_i/axi_ahci_regs_i/ahci_regs_i/bram_rdata_r[1]_i_1/O
net (fo=1, routed) 0.000 11.168 sata_top/ahci_top_i/axi_ahci_regs_i/ahci_regs_i_n_79
SLICE_X37Y147 FDRE r sata_top/ahci_top_i/axi_ahci_regs_i/bram_rdata_r_reg[1]/D
------------------------------------------------------------------- -------------------
(clock axihp_clk rise edge)
6.667 6.667 r
BUFGCTRL_X0Y23 BUFG 0.000 6.667 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.593 8.260 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.083 8.343 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 1.754 10.097 clocks393_i/hclk_i/hclk_pre
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.113 10.210 r clocks393_i/hclk_i/clk1x_i/O
net (fo=3868, routed) 1.272 11.482 sata_top/ahci_top_i/axi_ahci_regs_i/hclk
SLICE_X37Y147 FDRE r sata_top/ahci_top_i/axi_ahci_regs_i/bram_rdata_r_reg[1]/C
clock pessimism 0.317 11.799
clock uncertainty -0.071 11.727
SLICE_X37Y147 FDRE (Setup_fdre_C_D) 0.034 11.761 sata_top/ahci_top_i/axi_ahci_regs_i/bram_rdata_r_reg[1]
-------------------------------------------------------------------
required time 11.761
arrival time -11.168
-------------------------------------------------------------------
slack 0.593
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.038ns (arrival time - required time)
Source: sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/inreg_reg[8]/C
(rising edge-triggered cell FDRE clocked by axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns})
Destination: sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/ram_reg_0_15_6_11/RAMB/I
(rising edge-triggered cell RAMD32 clocked by axihp_clk {rise@0.000ns fall@3.333ns period=6.667ns})
Path Group: axihp_clk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (axihp_clk rise@0.000ns - axihp_clk rise@0.000ns)
Data Path Delay: 0.145ns (logic 0.091ns (62.668%) route 0.054ns (37.332%))
Logic Levels: 0
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.685ns
Source Clock Delay (SCD): 2.146ns
Clock Pessimism Removal (CPR): 0.528ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock axihp_clk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.666 0.666 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.050 0.716 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.774 1.490 clocks393_i/hclk_i/hclk_pre
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.026 1.516 r clocks393_i/hclk_i/clk1x_i/O
net (fo=3868, routed) 0.630 2.146 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/hclk
SLICE_X27Y156 FDRE r sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/inreg_reg[8]/C
------------------------------------------------------------------- -------------------
SLICE_X27Y156 FDRE (Prop_fdre_C_Q) 0.091 2.237 r sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/inreg_reg[8]/Q
net (fo=1, routed) 0.054 2.291 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/ram_reg_0_15_6_11/DIB0
SLICE_X26Y156 RAMD32 r sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/ram_reg_0_15_6_11/RAMB/I
------------------------------------------------------------------- -------------------
(clock axihp_clk rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.903 0.903 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
0.053 0.956 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
net (fo=1, routed) 0.843 1.799 clocks393_i/hclk_i/hclk_pre
BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.030 1.829 r clocks393_i/hclk_i/clk1x_i/O
net (fo=3868, routed) 0.856 2.685 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/ram_reg_0_15_6_11/WCLK
SLICE_X26Y156 RAMD32 r sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/ram_reg_0_15_6_11/RAMB/CLK
clock pessimism -0.528 2.157
SLICE_X26Y156 RAMD32 (Hold_ramd32_CLK_I)
0.096 2.253 sata_top/ahci_top_i/axi_ahci_regs_i/axibram_write_i/wdata_i/ram_reg_0_15_6_11/RAMB
-------------------------------------------------------------------
required time -2.253
arrival time 2.291
-------------------------------------------------------------------
slack 0.038
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: axihp_clk
Waveform(ns): { 0.000 3.333 }
Period(ns): 6.667
Sources: { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a GTXE2_CHANNEL/DRPCLK n/a 6.400 6.667 0.267 GTXE2_CHANNEL_X0Y0 sata_top/ahci_sata_layers_i/phy/gtx_wrap/gtxe2_channel_wrapper/gtx_unisims/DRPCLK
Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 6.667 153.333 PLLE2_ADV_X1Y3 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT0
Low Pulse Width Slow RAMD32/CLK n/a 0.910 3.333 2.423 SLICE_X38Y133 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_ram_reg_0_7_12_17/RAMA/CLK
High Pulse Width Slow RAMD32/CLK n/a 0.910 3.333 2.423 SLICE_X38Y134 sata_top/ahci_top_i/ahci_dma_i/ahci_dma_rd_fifo_i/fifo_ram_reg_0_7_42_47/RAMA/CLK
---------------------------------------------------------------------------------------------------
From Clock: clk_fb
To Clock: clk_fb
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 18.751ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk_fb
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 20.000 80.000 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: ddr3_clk
To Clock: ddr3_clk
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 0.279ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: ddr3_clk
Waveform(ns): { 0.000 1.250 }
Period(ns): 2.500
Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFR/I n/a 2.221 2.500 0.279 BUFR_X1Y8 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_bufr_i/I
Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 2.500 210.860 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1
---------------------------------------------------------------------------------------------------
From Clock: ddr3_clk_div
To Clock: ddr3_clk_div
Setup : 0 Failing Endpoints, Worst Slack 0.309ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.136ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 1.389ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.309ns (required time - arrival time)
Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[0]/C
(rising edge-triggered cell FDRE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_cmd_reg[1]/D
(rising edge-triggered cell FDRE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: ddr3_clk_div
Path Type: Setup (Max at Slow Process Corner)
Requirement: 5.000ns (ddr3_clk_div rise@5.000ns - ddr3_clk_div rise@0.000ns)
Data Path Delay: 4.490ns (logic 0.361ns (8.041%) route 4.129ns (91.959%))
Logic Levels: 1 (LUT6=1)
Clock Path Skew: -0.150ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.521ns = ( 8.521 - 5.000 )
Source Clock Delay (SCD): 3.927ns
Clock Pessimism Removal (CPR): 0.256ns
Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.156ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.575 1.575 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.088 1.663 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.106 2.769 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.377 3.146 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.781 3.927 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/clk_div
SLICE_X88Y103 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X88Y103 FDRE (Prop_fdre_C_Q) 0.308 4.235 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/dly_addr_r_reg[0]/Q
net (fo=62, routed) 4.129 8.364 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/dly_addr_r_reg[6][0]
SLICE_X117Y134 LUT6 (Prop_lut6_I5_O) 0.053 8.417 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_cmd[1]_i_1/O
net (fo=1, routed) 0.000 8.417 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_cmd[1]_i_1_n_0
SLICE_X117Y134 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_cmd_reg[1]/D
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div rise edge)
5.000 5.000 r
BUFGCTRL_X0Y23 BUFG 0.000 5.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.437 6.437 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.083 6.520 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 1.016 7.536 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.370 7.906 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.615 8.521 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/psincdec_reg
SLICE_X117Y134 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_cmd_reg[1]/C
clock pessimism 0.256 8.777
clock uncertainty -0.085 8.692
SLICE_X117Y134 FDRE (Setup_fdre_C_D) 0.034 8.726 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/cmd_addr_i/ld_dly_cmd_reg[1]
-------------------------------------------------------------------
required time 8.726
arrival time -8.417
-------------------------------------------------------------------
slack 0.309
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.136ns (arrival time - required time)
Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/ld_idly_reg[4]/C
(rising edge-triggered cell FDRE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre_reg[2]/D
(rising edge-triggered cell FDRE clocked by ddr3_clk_div {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: ddr3_clk_div
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (ddr3_clk_div rise@0.000ns - ddr3_clk_div rise@0.000ns)
Data Path Delay: 0.243ns (logic 0.130ns (53.531%) route 0.113ns (46.469%))
Logic Levels: 1 (LUT3=1)
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.738ns
Source Clock Delay (SCD): 1.424ns
Clock Pessimism Removal (CPR): 0.303ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.580 0.580 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.050 0.630 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.433 1.063 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.090 1.153 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.271 1.424 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/psincdec_reg_0
SLICE_X115Y133 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/ld_idly_reg[4]/C
------------------------------------------------------------------- -------------------
SLICE_X115Y133 FDRE (Prop_fdre_C_Q) 0.100 1.524 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/ld_idly_reg[4]/Q
net (fo=5, routed) 0.113 1.637 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[4].dq_i/dq_in_dly_i/ld_idly_reg[4][0]
SLICE_X114Y133 LUT3 (Prop_lut3_I1_O) 0.030 1.667 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre[2]_i_1__11/O
net (fo=1, routed) 0.000 1.667 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre[2]_i_1__11_n_0
SLICE_X114Y133 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre_reg[2]/D
------------------------------------------------------------------- -------------------
(clock ddr3_clk_div rise edge)
0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.796 0.796 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.053 0.849 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
net (fo=1, routed) 0.490 1.339 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_pre
BUFR_X1Y9 BUFR (Prop_bufr_I_O) 0.093 1.432 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/O
net (fo=753, routed) 0.306 1.738 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[4].dq_i/dq_in_dly_i/psincdec_reg
SLICE_X114Y133 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre_reg[2]/C
clock pessimism -0.303 1.435
SLICE_X114Y133 FDRE (Hold_fdre_C_D) 0.096 1.531 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/dq_block[4].dq_i/dq_in_dly_i/fdly_pre_reg[2]
-------------------------------------------------------------------
required time -1.531
arrival time 1.667
-------------------------------------------------------------------
slack 0.136
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: ddr3_clk_div
Waveform(ns): { 0.000 2.500 }
Period(ns): 5.000
Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFR/I n/a 2.221 5.000 2.779 BUFR_X1Y9 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/clk_div_bufr_i/I
Max Period n/a MMCME2_ADV/CLKOUT2 n/a 213.360 5.000 208.360 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2
Low Pulse Width Slow MMCME2_ADV/PSCLK n/a 1.111 2.500 1.389 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK
High Pulse Width Slow MMCME2_ADV/PSCLK n/a 1.111 2.500 1.389 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK
---------------------------------------------------------------------------------------------------
From Clock: ddr3_clk_ref
To Clock: ddr3_clk_ref
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: ddr3_clk_ref
Waveform(ns): { 0.000 2.500 }
Period(ns): 5.000
Sources: { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT5 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a IDELAYCTRL/REFCLK n/a 3.225 5.000 1.775 IDELAYCTRL_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK
Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 IDELAYCTRL_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/idelay_ctrl_i/idelay_ctrl_i/REFCLK
---------------------------------------------------------------------------------------------------
From Clock: ddr3_mclk
To Clock: ddr3_mclk
Setup : 0 Failing Endpoints, Worst Slack 0.179ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.026ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 1.389ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.179ns (required time - arrival time)
Source: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/wbuf_delay_reg[3]/C
(rising edge-triggered cell FDSE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns})
Destination: mcntrl393_i/memctrl16_i/mcontr_sequencer_i/run_w_d_negedge_reg/D
(falling edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns})
Path Group: ddr3_mclk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.500ns (ddr3_mclk fall@3.750ns - ddr3_mclk rise@1.250ns)
Data Path Delay: 2.183ns (logic 0.503ns (23.047%) route 1.680ns (76.953%))
Logic Levels: 2 (LUT4=1 SRL16E=1)
Clock Path Skew: -0.023ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.446ns = ( 8.196 - 3.750 )
Source Clock Delay (SCD): 4.801ns = ( 6.051 - 1.250 )
Clock Pessimism Removal (CPR): 0.332ns
Clock Uncertainty: 0.085ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.156ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
1.250 1.250 r
BUFGCTRL_X0Y23 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.575 2.825 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.088 2.913 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 1.628 4.541 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.120 4.661 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=33206, routed) 1.390 6.051 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/dbg1_reg
SLICE_X68Y108 FDSE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/wbuf_delay_reg[3]/C
------------------------------------------------------------------- -------------------
SLICE_X68Y108 FDSE (Prop_fdse_C_Q) 0.269 6.320 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/wbuf_delay_reg[3]/Q
net (fo=3, routed) 0.665 6.985 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/buf_wchn_dly_i/bit_block[0].dly01_16_i/Q[3]
SLICE_X66Y108 LUT4 (Prop_lut4_I3_O) 0.066 7.051 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/buf_wchn_dly_i/bit_block[0].dly01_16_i/sr_reg[0]_srl1_i_5/O
net (fo=6, routed) 0.542 7.594 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/buf_wchn_dly_i/bit_block[5].dly01_16_i/wbuf_delay_reg[2]
SLICE_X66Y111 SRL16E (Prop_srl16e_A3_Q) 0.168 7.762 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/buf_wchn_dly_i/bit_block[5].dly01_16_i/sr_reg[0]_srl1/Q
net (fo=1, routed) 0.472 8.234 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/run_w_d
SLICE_X67Y111 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/run_w_d_negedge_reg/D
------------------------------------------------------------------- -------------------
(clock ddr3_mclk fall edge)
3.750 3.750 f
BUFGCTRL_X0Y23 BUFG 0.000 3.750 f clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.437 5.187 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.083 5.270 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 1.544 6.814 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.113 6.927 f mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=33206, routed) 1.269 8.196 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/dbg1_reg
SLICE_X67Y111 FDRE r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/run_w_d_negedge_reg/C (IS_INVERTED)
clock pessimism 0.332 8.528
clock uncertainty -0.085 8.443
SLICE_X67Y111 FDRE (Setup_fdre_C_D) -0.030 8.413 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/run_w_d_negedge_reg
-------------------------------------------------------------------
required time 8.413
arrival time -8.234
-------------------------------------------------------------------
slack 0.179
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.026ns (arrival time - required time)
Source: mcntrl393_i/mcntrl_tiled_rw_chn4_i/row_col_r_reg[19]/C
(rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns})
Destination: mcntrl393_i/cmd_encod_tiled_mux_i/row_r_reg[12]/D
(rising edge-triggered cell FDRE clocked by ddr3_mclk {rise@1.250ns fall@3.750ns period=5.000ns})
Path Group: ddr3_mclk
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (ddr3_mclk rise@1.250ns - ddr3_mclk rise@1.250ns)
Data Path Delay: 0.273ns (logic 0.128ns (46.965%) route 0.145ns (53.035%))
Logic Levels: 1 (LUT6=1)
Clock Path Skew: 0.187ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.272ns = ( 3.522 - 1.250 )
Source Clock Delay (SCD): 1.798ns = ( 3.048 - 1.250 )
Clock Pessimism Removal (CPR): 0.287ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
1.250 1.250 r
BUFGCTRL_X0Y23 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.580 1.830 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.050 1.880 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 0.559 2.439 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 2.465 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=33206, routed) 0.583 3.048 mcntrl393_i/mcntrl_tiled_rw_chn4_i/clk
SLICE_X92Y99 FDRE r mcntrl393_i/mcntrl_tiled_rw_chn4_i/row_col_r_reg[19]/C
------------------------------------------------------------------- -------------------
SLICE_X92Y99 FDRE (Prop_fdre_C_Q) 0.100 3.148 r mcntrl393_i/mcntrl_tiled_rw_chn4_i/row_col_r_reg[19]/Q
net (fo=1, routed) 0.145 3.293 mcntrl393_i/mcntrl_tiled_rw_chn4_i/tiled_rw_chn4_row[12]
SLICE_X93Y100 LUT6 (Prop_lut6_I2_O) 0.028 3.321 r mcntrl393_i/mcntrl_tiled_rw_chn4_i/row_r[12]_i_1__0/O
net (fo=1, routed) 0.000 3.321 mcntrl393_i/cmd_encod_tiled_mux_i/row_col_r_reg[21][12]
SLICE_X93Y100 FDRE r mcntrl393_i/cmd_encod_tiled_mux_i/row_r_reg[12]/D
------------------------------------------------------------------- -------------------
(clock ddr3_mclk rise edge)
1.250 1.250 r
BUFGCTRL_X0Y23 BUFG 0.000 1.250 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 0.796 2.046 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/axi_clk
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT3)
0.053 2.099 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
net (fo=1, routed) 0.623 2.722 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_pre
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.030 2.752 r mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mclk_i/O
net (fo=33206, routed) 0.770 3.522 mcntrl393_i/cmd_encod_tiled_mux_i/clk
SLICE_X93Y100 FDRE r mcntrl393_i/cmd_encod_tiled_mux_i/row_r_reg[12]/C
clock pessimism -0.287 3.235
SLICE_X93Y100 FDRE (Hold_fdre_C_D) 0.060 3.295 mcntrl393_i/cmd_encod_tiled_mux_i/row_r_reg[12]
-------------------------------------------------------------------
required time -3.295
arrival time 3.321
-------------------------------------------------------------------
slack 0.026
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: ddr3_mclk
Waveform(ns): { 1.250 3.750 }
Period(ns): 5.000
Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.495 5.000 2.505 RAMB36_X0Y10 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_histogram_0_i/sens_hist_ram_snglclk_32_i/ramt_var_w_var_r_even_i/RAMB36E1_i/CLKBWRCLK
Max Period n/a MMCME2_ADV/CLKOUT3 n/a 213.360 5.000 208.360 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3
Low Pulse Width Slow MMCME2_ADV/PSCLK n/a 1.111 2.500 1.389 MMCME2_ADV_X1Y3 sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK
High Pulse Width Slow MMCME2_ADV/PSCLK n/a 1.111 2.500 1.389 MMCME2_ADV_X0Y1 sensors393_i/sensor_channel_block[2].sensor_channel_i/sens_parallel12_i/mmcm_phase_cntr_i/MMCME2_ADV_i/PSCLK
---------------------------------------------------------------------------------------------------
From Clock: ddr3_sdclk
To Clock: ddr3_sdclk
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 1.092ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: ddr3_sdclk
Waveform(ns): { 0.000 1.250 }
Period(ns): 2.500
Sources: { mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFIO/I n/a 1.408 2.500 1.092 BUFIO_X1Y9 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/iclk_bufio_i/I
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 2.500 210.860 MMCME2_ADV_X1Y2 mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0
---------------------------------------------------------------------------------------------------
From Clock: multi_clkfb
To Clock: multi_clkfb
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 18.751ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: multi_clkfb
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a PLLE2_ADV/CLKFBOUT n/a 1.249 20.000 18.751 PLLE2_ADV_X1Y3 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBOUT
Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 20.000 32.633 PLLE2_ADV_X1Y3 clocks393_i/pll_base_i/PLLE2_ADV_i/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: sclk
To Clock: sclk
Setup : 0 Failing Endpoints, Worst Slack 4.219ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.044ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 4.090ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 4.219ns (required time - arrival time)
Source: event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C
(rising edge-triggered cell FDRE clocked by sclk {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D
(falling edge-triggered cell FDRE clocked by sclk {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: sclk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 5.000ns (sclk fall@5.000ns - sclk rise@0.000ns)
Data Path Delay: 0.675ns (logic 0.308ns (45.637%) route 0.367ns (54.363%))
Logic Levels: 0
Clock Path Skew: -0.027ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 5.011ns = ( 10.011 - 5.000 )
Source Clock Delay (SCD): 5.494ns
Clock Pessimism Removal (CPR): 0.456ns
Clock Uncertainty: 0.075ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.133ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock sclk rise edge) 0.000 0.000 r
BUFGCTRL_X0Y23 BUFG 0.000 0.000 r clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.784 1.784 clocks393_i/pll_base_i/axi_clk
PLLE2_ADV_X1Y3 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT3)
0.088 1.872 r clocks393_i/pll_base_i/PLLE2_ADV_i/CLKOUT3
net (fo=1, routed) 1.868 3.740 clocks393_i/sync_clk_i/sync_clk_pre
BUFGCTRL_X0Y22 BUFG (Prop_bufg_I_O) 0.120 3.860 r clocks393_i/sync_clk_i/clk1x_i/O
net (fo=1347, routed) 1.634 5.494 event_logger_i/i_imu_spi/camsync_clk
SLICE_X102Y158 FDRE r event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/C
------------------------------------------------------------------- -------------------
SLICE_X102Y158 FDRE (Prop_fdre_C_Q) 0.308 5.802 r event_logger_i/i_imu_spi/sngl_wire_stb_reg[0]/Q
net (fo=2, routed) 0.367 6.169 event_logger_i/i_imu_spi/sngl_wire_stb_reg_n_0_[0]
SLICE_X104Y158 FDRE r event_logger_i/i_imu_spi/sngl_wire_r_reg[1]/D
------------------------------------------------------------------- -------------------
(clock sclk fall edge) 5.000 5.000 f
BUFGCTRL_X0Y23 BUFG 0.000 5.000 f clocks393_i/bufg_axi_aclk_i/O
net (fo=738, routed) 1.593 6.593 clocks393_i/pll_base_i/axi_clk