{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":668351602,"defaultBranch":"master","name":"seL4","ownerLogin":"CTSRD-CHERI","currentUserCanPush":false,"isFork":true,"isEmpty":false,"createdAt":"2023-07-19T15:43:51.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/810768?v=4","public":true,"private":false,"isOrgOwned":true},"refInfo":{"name":"","listCacheKey":"v0:1727086388.0","currentOid":""},"activityList":{"items":[{"before":"d19844e43e27186253252369ad23d9dc37291a3c","after":"6765898e71af6c969481fae3250030fd82e9a971","ref":"refs/heads/cheri","pushedAt":"2024-09-23T17:20:29.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"types: Use paddr_to_pptr in favour of ptrFromPAddr\n\nThis commit favours using paddr_to_pptr, pptr_to_paddr, and\nkpptr_to_paddr over addrFromPPtr, addrFromKPPtr, and ptrFromPAddr,\nrespectively. The reason is mainly for consistency all over the seL4\ncode. Furthermore, the favoured macros now cast to uintptr_t which\nshould be fine to perform generic pointer arithemtic on (unlike void *).\nFinally, there will be no need to perform casting from the callees,\nand this will get rid of compiler warnings such as\n\"incompatible pointer to integer conversion\" and,\n\"makes integer from pointer without a cast.\"\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"types: Use paddr_to_pptr in favour of ptrFromPAddr"}},{"before":"ccdb5eb16094239eb8d0a1520894574c331afc94","after":"d19844e43e27186253252369ad23d9dc37291a3c","ref":"refs/heads/cheri","pushedAt":"2024-09-23T17:11:01.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"types: Use paddr_to_pptr in favour of ptrFromPAddr\n\nThis commit favours using paddr_to_pptr, pptr_to_paddr, and\nkpptr_to_paddr over addrFromPPtr, addrFromKPPtr, and ptrFromPAddr,\nrespectively. The reason is mainly for consistency all over the seL4\ncode. Furthermore, the favoured macros now cast to uintptr_t which\nshould be fine to perform generic pointer arithemtic on (unlike void *).\nFinally, there will be no need to perform casting from the callees,\nand this will get rid of compiler warnings such as\n\"incompatible pointer to integer conversion\" and,\n\"makes integer from pointer without a cast.\"\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"types: Use paddr_to_pptr in favour of ptrFromPAddr"}},{"before":"efc8a3a86cda353f47a3803320f68767feec619a","after":"ccdb5eb16094239eb8d0a1520894574c331afc94","ref":"refs/heads/cheri","pushedAt":"2024-09-23T17:03:18.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"types: Use paddr_to_pptr in favour of ptrFromPAddr\n\nThis commit favours using paddr_to_pptr, pptr_to_paddr, and\nkpptr_to_paddr over addrFromPPtr, addrFromKPPtr, and ptrFromPAddr,\nrespectively. The reason is mainly for consistency all over the seL4\ncode. Furthermore, the favoured macros now cast to uintptr_t which\nshould be fine to perform generic pointer arithemtic on (unlike void *).\nFinally, there will be no need to perform casting from the callees,\nand this will get rid of compiler warnings such as\n\"incompatible pointer to integer conversion\" and,\n\"makes integer from pointer without a cast.\"\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"types: Use paddr_to_pptr in favour of ptrFromPAddr"}},{"before":"f2b4193b09acb06cee8b2230ab9d817a4417ef4f","after":"efc8a3a86cda353f47a3803320f68767feec619a","ref":"refs/heads/cheri","pushedAt":"2024-09-23T15:44:24.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"types: Use paddr_to_pptr in favour of ptrFromPAddr\n\nThis commit favours using paddr_to_pptr, pptr_to_paddr, and\nkpptr_to_paddr over addrFromPPtr, addrFromKPPtr, and ptrFromPAddr,\nrespectively. The reason is mainly for consistency all over the seL4\ncode. Furthermore, the favoured macros now cast to uintptr_t which\nshould be fine to perform generic pointer arithemtic on (unlike void *).\nFinally, there will be no need to perform casting from the callees,\nand this will get rid of compiler warnings such as\n\"incompatible pointer to integer conversion\" and,\n\"makes integer from pointer without a cast.\"\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"types: Use paddr_to_pptr in favour of ptrFromPAddr"}},{"before":"82f490a33cf11c916cf5f83202ff196219d875f3","after":"f2b4193b09acb06cee8b2230ab9d817a4417ef4f","ref":"refs/heads/cheri","pushedAt":"2024-09-23T15:32:45.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"types: Use paddr_to_pptr in favour of ptrFromPAddr\n\nThis commit favours using paddr_to_pptr, pptr_to_paddr, and\nkpptr_to_paddr over addrFromPPtr, addrFromKPPtr, and ptrFromPAddr,\nrespectively. The reason is mainly for consistency all over the seL4\ncode. Furthermore, the favoured macros now cast to uintptr_t which\nshould be fine to perform generic pointer arithemtic on (unlike void *).\nFinally, there will be no need to perform casting from the callees,\nand this will get rid of compiler warnings such as\n\"incompatible pointer to integer conversion\" and,\n\"makes integer from pointer without a cast.\"\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"types: Use paddr_to_pptr in favour of ptrFromPAddr"}},{"before":"2cd815180a837f837459ac01bb49ce35341928cc","after":"82f490a33cf11c916cf5f83202ff196219d875f3","ref":"refs/heads/cheri","pushedAt":"2024-09-23T12:07:38.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"[cheri][riscv] architecture-dependent purecap port\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"[cheri][riscv] architecture-dependent purecap port"}},{"before":"3c801219cb05709f1800cb9f1ec33325b15fe2c4","after":"2cd815180a837f837459ac01bb49ce35341928cc","ref":"refs/heads/cheri","pushedAt":"2024-09-23T11:36:02.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"[cheri][riscv] architecture-dependent purecap port\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"[cheri][riscv] architecture-dependent purecap port"}},{"before":"f4e4d1b8f251b68a6f1104a0bcb21c6c9a9ce948","after":"3c801219cb05709f1800cb9f1ec33325b15fe2c4","ref":"refs/heads/cheri","pushedAt":"2024-09-23T11:29:16.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"fixup morello","shortMessageHtmlLink":"fixup morello"}},{"before":null,"after":"f4e4d1b8f251b68a6f1104a0bcb21c6c9a9ce948","ref":"refs/heads/cheri","pushedAt":"2024-09-23T10:13:08.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"[cheri][riscv] architecture-dependent purecap port\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"[cheri][riscv] architecture-dependent purecap port"}},{"before":null,"after":"a87737b0eb95cb02e2d592a5da4cdbe2f5a2c661","ref":"refs/heads/morello_aarch64","pushedAt":"2024-02-05T10:21:00.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"morello: Add a new Morello hardware board platform\n\nThis commit adds a new Arm's Morello board platform to seL4\nalso known as morello-soc. It only supports AArch64 mode\nwithout CHERI support and could be built with either GCC\nor LLVM/lld.\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"morello: Add a new Morello hardware board platform"}},{"before":"47e54453df608c0cb1bc92a64ea14ed19b63d971","after":null,"ref":"refs/heads/48bit_pa","pushedAt":"2024-02-05T10:17:12.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"}},{"before":"561ce27b3252f6620370b5fea4579ec78fa5e481","after":"ca3617c403c96f8430f6cf5d43825a52826640b7","ref":"refs/heads/pr1_morello_aarch64","pushedAt":"2024-01-29T11:51:51.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"morello: Add a new FVP platform\n\nThis commit adds a new Arm's Morello FVP platform to seL4. It only\nsupports AArch64 mode without CHERI support and could be built with\neither GCC or LLVM/lld. Morello FVP could be downloaded from [1] or\nbuilt with cheribuild, and run the same way as the existing seL4's\nFVP platform.\n\n[1] https://developer.arm.com/downloads/-/arm-ecosystem-fvps\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"morello: Add a new FVP platform"}},{"before":null,"after":"e11efb28260350c354624b5513b31b89202e5f53","ref":"refs/heads/pr2_morello_aarch64","pushedAt":"2024-01-29T11:49:44.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"morello: Add a new Morello hardware board platform\n\nThis commit adds a new Arm's Morello board platform to seL4\nalso known as morello-soc. It only supports AArch64 mode\nwithout CHERI support and could be built with either GCC\nor LLVM/lld.\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"morello: Add a new Morello hardware board platform"}},{"before":null,"after":"561ce27b3252f6620370b5fea4579ec78fa5e481","ref":"refs/heads/pr1_morello_aarch64","pushedAt":"2024-01-29T11:24:14.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"morello: Add a new FVP platform\n\nThis commit adds a new Arm's Morello FVP platform to seL4. It only\nsupport AArch64 mode without CHERI support and could be builti with\neither GCC or LLVM/lld. Morello FVP could be downloaded from [1] or\nbuilt with cheribuild, and run the same way as the existing seL4's\nFVP platform.\n\n[1] https://developer.arm.com/downloads/-/arm-ecosystem-fvps\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"morello: Add a new FVP platform"}},{"before":"8360a5855748218ad93a0b750e0b8f7b84fcf66e","after":"47e54453df608c0cb1bc92a64ea14ed19b63d971","ref":"refs/heads/48bit_pa","pushedAt":"2024-01-16T11:16:49.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"Zero capPtr for device untyped capabilities\n\nIf the untyped cap is a device memory, the kernel has no mapping\nfor it and hence pptr does not make sense and is not used.\nZeroing pptr here makes it clear that this untyped is not\nused/mapped, and avoids an assertion error in the generated\ncap_untyped_cap_new where it checks if the pptr is canonical\nvirtual address regardless if it is device untyped or not,\nwhich may fail on systems that have 48-bit physical address\nspace or larger.\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"Zero capPtr for device untyped capabilities"}},{"before":"a4f3f2c9bda0f22e0cd2d7d80b0887e6d9c2f266","after":"8360a5855748218ad93a0b750e0b8f7b84fcf66e","ref":"refs/heads/48bit_pa","pushedAt":"2024-01-16T11:10:25.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"Zero capPtr for device untyped capabilities\n\nIf the untyped cap is a device memory, the kernel has no mapping\nfor it and hence pptr does not make sense and is not used.\nZeroing pptr here makes it clear that this untyped is not\nused/mapped, and avoids an assertion error in the generated\ncap_untyped_cap_new where it checks if the pptr is canonical\nvirtual address regardless if it is device untyped or not,\nwhich may fail on systems that have 48-bit physical address\nspace or larger.\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"Zero capPtr for device untyped capabilities"}},{"before":null,"after":"a4f3f2c9bda0f22e0cd2d7d80b0887e6d9c2f266","ref":"refs/heads/48bit_pa","pushedAt":"2024-01-16T11:03:35.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"Zero capPtr for device untyped capabilities\n\nIf the untyped cap is a device memory, the kernel has no mapping\nfor it and hence pptr does not make sense and is not used.\nZeroing pptr here makes it clear that this untyped is not\nused/mapped, and avoids an assertion error in the generated\ncap_untyped_cap_new where it checks if the pptr is canonical\nvirtual address regardless if it is device untyped or not,\nwhich may fail on systems that have 48-bit physical address\nspace or larger.\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"Zero capPtr for device untyped capabilities"}},{"before":"5ea43472621d3d8791d1fe9b053bf4916a0dba6e","after":"ef41e6e657265d4bdffcd1f7f54008baa93a762a","ref":"refs/heads/pr_morello_aarch64","pushedAt":"2024-01-12T15:10:43.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"qemu-morello: Add a new platform\n\nCurrently only supports running vanilla AArch64 code built with\nLLVM/lld on QEMU's morello from the CHERI group [1]\n\n[1] https://github.com/CTSRD-CHERI/qemu\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"qemu-morello: Add a new platform"}},{"before":"7127be896b0eb7a1c2168486e1c42af84c9d2ed4","after":"5ea43472621d3d8791d1fe9b053bf4916a0dba6e","ref":"refs/heads/pr_morello_aarch64","pushedAt":"2024-01-12T15:08:52.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"qemu-morello: Add a new platform\n\nCurrently only supports running vanilla AArch64 code built with\nLLVM/lld on QEMU's morello from the CHERI group [1]\n\n[1] https://github.com/CTSRD-CHERI/qemu\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"qemu-morello: Add a new platform"}},{"before":"e768217c24496aaa458264beedc489b7831f572d","after":"7127be896b0eb7a1c2168486e1c42af84c9d2ed4","ref":"refs/heads/pr_morello_aarch64","pushedAt":"2024-01-12T14:48:44.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"qemu-morello: Add a new platform\n\nCurrently only supports running vanilla AArch64 code built with\nLLVM/lld on QEMU's morello from the CHERI group [1]\n\n[1] https://github.com/CTSRD-CHERI/qemu\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"qemu-morello: Add a new platform"}},{"before":"1a0cfeacb8fa3983509ce03d863c1b7ee9cacd67","after":"e768217c24496aaa458264beedc489b7831f572d","ref":"refs/heads/pr_morello_aarch64","pushedAt":"2024-01-12T14:38:59.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"qemu-morello: Add a new platform\n\nCurrently only supports running vanilla AArch64 code built with\nLLVM/lld on QEMU's morello from the CHERI group [1]\n\n[1] https://github.com/CTSRD-CHERI/qemu\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"qemu-morello: Add a new platform"}},{"before":"1448f988344fd929db3cd48829fdc5151ec3b8af","after":"1a0cfeacb8fa3983509ce03d863c1b7ee9cacd67","ref":"refs/heads/pr_morello_aarch64","pushedAt":"2024-01-08T15:39:05.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"qemu-morello: Add a new platform\n\nCurrently only supports running vanilla AArch64 code built with\nLLVM/lld on QEMU's morello from the CHERI group [1]\n\n[1] https://github.com/CTSRD-CHERI/qemu\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"qemu-morello: Add a new platform"}},{"before":null,"after":"1448f988344fd929db3cd48829fdc5151ec3b8af","ref":"refs/heads/pr_morello_aarch64","pushedAt":"2024-01-08T15:11:59.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"qemu-morello: Add a new platform\n\nCurrently only supports running vanilla AArch64 code built with\nLLVM/lld on QEMU's morello from the CHERI group [1]\n\n[1] https://github.com/CTSRD-CHERI/qemu\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"qemu-morello: Add a new platform"}},{"before":"f50ce328d0b1fd5bc05403a1997ebcfb45655ff7","after":"3433141497c2bcbe6a153a9ff89d9cb646313c0d","ref":"refs/heads/riscv_fastpath","pushedAt":"2023-11-01T09:59:32.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"riscv: place traps and fastpath code adjacently\n\nFollow Arm's code where it tries to place traps and vector\ncode adjacently in a 4KiB page to optimise performance\n(through spatial cache locality).\n\nCloses #1091\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"riscv: place traps and fastpath code adjacently"}},{"before":"ba34d6f18ff66821ee6262ea0cfeec1002d6026f","after":"f50ce328d0b1fd5bc05403a1997ebcfb45655ff7","ref":"refs/heads/riscv_fastpath","pushedAt":"2023-10-31T11:20:01.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"riscv: place traps and fastpath code adjacently\n\nFollow Arm's code where it tries to place traps and vector\ncode adjacently in a 4KiB page to optimise performance\n(through spatial cache locality).\n\nCloses #1091\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"riscv: place traps and fastpath code adjacently"}},{"before":"49f4ddfc8c20249b7a114a4cc3baa42f5f9eaa6c","after":"b9b36e584a75df99be6e65ef68ef7a5daba61d70","ref":"refs/heads/master","pushedAt":"2023-10-30T15:52:39.000Z","pushType":"push","commitsCount":59,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"cmake: remove mention of undone change in CHANGES\n\ngen_config.h files are no longer generated at build time rather than\nconfigure time. This is a return to the behavior of the last release.\nRemove mention of the temporary change.\n\nSigned-off-by: Nick Spinale ","shortMessageHtmlLink":"cmake: remove mention of undone change in CHANGES"}},{"before":null,"after":"ba34d6f18ff66821ee6262ea0cfeec1002d6026f","ref":"refs/heads/riscv_fastpath","pushedAt":"2023-08-14T13:50:39.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"riscv: place traps and fastpath code adjacently\n\nFollow Arm's code where it tries to place traps and vector\ncode adjacently in a 4KiB page to optimise performance\n(through spatial cache locality).\n\nCloses #1091\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"riscv: place traps and fastpath code adjacently"}},{"before":"d0c88efc4e85e5f1f1723d40d2346ea42c40f578","after":"9d9c4c17c3e73291a537c53f8d993d444be4cb7a","ref":"refs/heads/lld","pushedAt":"2023-08-14T09:09:32.000Z","pushType":"force_push","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"Add \"ax\" flags to .section directives in assembly\n\nThis commit fixes a linking error when using LLVM's lld.\n\nllvm-as doesn't assume or assign section flags for input section if\nnot specified. This will make the section non-allocatable and put\ninto a none segment and trigger relocation linking errors against\nsymbols in non-allocatble sections.\n\nFor example, when building with LLVM/lld for AArch64, the following\nerror occurs:\n(traps.S.obj:(function arm_vector_table: .vectors+0x0): has non-ABS\nrelocation R_AARCH64_JUMP26 against symbol 'invalid_vector_entry')\nThis does not happen with ld.bfd (GNU's linker) as it seems to allow\nrelocations against symbols in non-allocatable sections.\n\nThe GNU's assembler documentation states that:\n\"If no flags are specified, the default flags depend upon the\nsection name. If the section name is not recognized, the default\nwill be for the section to have none of the above flags: it will\nnot be allocated in memory, nor writable, nor executable.\nThe section will contain data. [1]\"\n\nThis commit explicitly sets .section flags in assembly to avoid\nthis error and for better intentionality (and good practice)\nwithout relying on toolchains handling flags and linkage differently.\n\n[1] https://sourceware.org/binutils/docs/as/Section.html\n\nSponsored by: DARPA.\n\nSigned-off-by: Hesham Almatary ","shortMessageHtmlLink":"Add \"ax\" flags to .section directives in assembly"}},{"before":"4535bccc972a5e19b0d617bc138ba0239bd33aff","after":null,"ref":"refs/heads/riscv_fix","pushedAt":"2023-08-12T10:48:25.000Z","pushType":"branch_deletion","commitsCount":0,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"}},{"before":"177c16e8ad39eacafd04126853582a2e35adeba0","after":"4535bccc972a5e19b0d617bc138ba0239bd33aff","ref":"refs/heads/riscv_fix","pushedAt":"2023-08-11T11:10:34.000Z","pushType":"push","commitsCount":10,"pusher":{"login":"heshamelmatary","name":"Hesham Almatary","path":"/heshamelmatary","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/1679930?s=80&v=4"},"commit":{"message":"Merge branch 'master' into riscv_fix","shortMessageHtmlLink":"Merge branch 'master' into riscv_fix"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"Y3Vyc29yOnYyOpK7MjAyNC0wOS0yM1QxNzoyMDoyOS4wMDAwMDBazwAAAAS-QLFB","startCursor":"Y3Vyc29yOnYyOpK7MjAyNC0wOS0yM1QxNzoyMDoyOS4wMDAwMDBazwAAAAS-QLFB","endCursor":"Y3Vyc29yOnYyOpK7MjAyMy0wOC0xMVQxMToxMDozNC4wMDAwMDBazwAAAANoyFbW"}},"title":"Activity ยท CTSRD-CHERI/seL4"}