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PDD2.dcDisASM
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PDD2.dcDisASM
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Header ;Tandy PDD2 firmware reverse engineering
Header ;By BiggRanger
orig 0xF000
FileIn c:\dcDisASM\PDD2\PDD2.BIN
FileOut c:\dcDisasm\PDD2\PDD2.ASM
;FileOptions EPROM boot loader (TMS320 only)
;file out can be .ASM, .RTF, .HTML
include c:\dcDisasm\CPU_INC\6301.INC
include c:\dcDisasm\PDD2\PDD2_Misc.inc
include c:\dcDisasm\PDD2\PDD2_Tables.inc
;flag asciiOnly ;only prints ascii characters in output
;flag colorJump green
;flag colorCall purple
;flag colorReturn red
;flag colorBox brown
;flag colorCode black
;flag colorValues orange
;flag colorLabels cyan
;flag colorComment green
;flag noSymbolTable
;flag noJumpLines
flag radixRepresentationCPP ;Intel, CPP, or Motorola, this only affects output.
flag showOpCodeHEX
flag showOpCodeASCII
;flag showMnemonicComments
;TYPE = byte, word, dword, qword
;REPRESENTATION = asc, hex, dec, bin
;CODE address label [COMMENT]
;IOLABEL ioAddress label [COMMENT]
;DATA address TYPE REPRESENTATION [LABEL [COMMENT]]
;TABLE addressStart length TYPE [REPRESENTATION [LABEL [COMMENT]]]]
;BYTEARRAY addressStart length REPRESENTATION [COMMENT]
;COMMENT adderss COMMENT
;VIEW address REPRESENTATION [COMMENT]
;BOX addressStart addressEnd [COMMENT]
;IGNORE addressStart addressEnd [COMMENT]
;----------------------------------------------------------
;Memory Map of PDD (using mode 6):
;----------------------------------------------------------
;0000-001F Internal Registers (see below)
;0080-00FF Internal RAM
;4000-4003 CPLD (Glue Logic + Hardware IO Control)
;8000-87FF External RAM (2K)
;F000-FFFF Internal ROM (4K)
;----------------------------------------------------------
;I/O ports of PDD (using mode 6):
;Port.Bit I/O Pin# ID Function
;----------------------------------------------------------
;Port1.B0 Input Pin18 P10 CTS
;Port1.B1 Input Pin19 P11 DSR
;Port1.B2 Output Pin20 P12 RTS
;Port1.B3 Output Pin22 P13 DTR
;Port1.B4 Output Pin23 P14 Alarm
;Port1.B5 Output Pin24 P15 WC on R/W module
;Port1.B6 Output Pin25 P16 Drives LED1
;Port1.B7 Output Pin26 P17 Scan
;Port2.B0 Output Pin11 P20 Serial Output enable, Mode (pulled Low)
;Port2.B1 Input Pin12 P21 Mode (pulled Hi)
;Port2.B2 Input Pin13 P22 (SCI) CLKOUT from CPLD for BAUD rate (start Hi)
;Port2.B3 Input Pin14 P23 (SCI) /RXD
;Port2.B4 Output Pin15 P24 (SCI) /TXD
;Port2.B5 N/A
;Port2.B6 N/A
;Port2.B7 N/A
;Port3.B0 I/O Pin51 P30 AD0
;Port3.B1 I/O Pin50 P31 AD1
;Port3.B2 I/O Pin45 P32 AD2
;Port3.B3 I/O Pin44 P33 AD3
;Port3.B4 I/O Pin43 P34 AD4
;Port3.B5 I/O Pin42 P35 AD5
;Port3.B6 I/O Pin41 P36 AD6
;Port3.B7 I/O Pin40 P37 AD7
;Port4.B0 I/O Pin37 P40 A8
;Port4.B1 I/O Pin36 P41 A9
;Port4.B2 I/O Pin35 P42 A10
;Port4.B3 Input Pin32 P43 A11 E1 *Config jumper pulled high
;Port4.B4 Input Pin31 P44 A12 E2 *Config jumper pulled high
;Port4.B5 Input Pin30 P45 A13 E3 *Config jumper pulled high
;Port4.B6 I/O Pin29 P46 A14 *CS1 on CPLD
;Port4.B7 I/O Pin28 P47 A15 *CS0 on CPLD
;Idle address lines on port 4 can be assigned as inputs
;----------------------------------------------------------
;----------------------------------------------------------
;Map for CPLD
;----------------------------------------------------------
data 0x4000 byte hex (CPLD)4000 ;set = stepper motor???
data 0x4001 byte hex (CPLD)4001 ;get = 1111_0000 dip switches, set = 1111_0000 BAUD clock
data 0x4002 byte hex (CPLD)4002
data 0x4003 byte hex (CPLD)4003
;----------------------------------------------------------
;----------------------------------------------------------
;Map for Internal RAM
;----------------------------------------------------------
data 0x0080 byte hex (RAM_INT)BAUD_Setting
data 0x0081 word hex (RAM_INT)StackPointerStorage ;Store stack pointer when computing checksum
data 0x0083 byte hex (RAM_INT)Brian83 ;TPDD2 backup.ba (sets to 0x00)
data 0x0084 byte hex (RAM_INT)Brian84 ;Reset drive status on pg 102 (sets to 0xFF)
data 0x008A byte hex (RAM_INT)SerDatRX_1
data 0x008B byte hex (RAM_INT)CPLD_Switch_0
data 0x0090 byte hex (RAM_INT)SerDatTX_1
data 0x0093 byte hex (RAM_INT)PCB_ConfigSwitchesE1E2E3
data 0x0094 byte hex (RAM_INT)Brian94 ;Reset drive status on pg 102 (sets to 0x0F)
data 0x0096 byte hex (RAM_INT)Brian96 ;Reset drive status on pg 102 (sets to 0x0F), TPDD2 backup.ba (sets to 0x00)
data 0x0099 word hex (RAM_INT)DataPacket_Data
data 0x009B byte hex (RAM_INT)Checksum_Temp_A
data 0x009C byte hex (RAM_INT)Checksum_Temp_B
data 0x009F byte hex (RAM_INT)BAUD_DelayLoop
data 0x00A0 byte hex (RAM_INT)SerDatTX_3
data 0x00A8 byte hex (RAM_INT)SerDatRX_2
data 0x00B5 byte hex (RAM_INT)Checksum_Value
;----------------------------------------------------------
;----------------------------------------------------------
;Map for External RAM
;----------------------------------------------------------
code 0x8013 (RAM_EXT)ExternalProgram ;Start Code Execution
data 0x87FF byte hex (RAM_EXT)Stack ;Top of Stack
;----------------------------------------------------------
;**********************************************************
;start documenting code
;**********************************************************
;----------------------------------------------------------
;Startup and initalization
;----------------------------------------------------------
box 0xF000 0xF02D ;Startup and initalization
code 0xF000 ProgramStart ;set stack to 87FF (top of EXT RAM)
view 0xF003 binary ;set data for port 1 and port 2
view 0xF008 binary ;set direction for port 1 and port 2
view 0xF00D binary ;set direction for port 3 and port 4
view 0xF015 binary
view 0xF01F binary
view 0xF024 binary
;----------------------------------------------------------
;----------------------------------------------------------
;BAUD Rate Setup
;----------------------------------------------------------
box 0xF030 0xF054 ;BAUD Rate Setup
comment 0xF030 ;get switch settings from CPLD
view 0xF034 binary ;mask bits - only look at 2 MSB
comment 0xF036 ;rotate through carry 0000_1100
comment 0xF03A ;BAUD table - 7 entries
comment 0xF040 ;Table 0, 2, 4, 6
comment 0xF042 ;send this value to the CPLD, this is the clock divider for the SIO clock
comment 0xF045 ;Table 1, 3, 5, 7
view 0xF049 binary ;look at bit 6 from (CPLD)4001
comment 0xF04D ;set RAM to FF
view 0xF050 binary ;look at bit 5 from CPLD
comment 0xF054 ;set MSB high
;----------------------------------------------------------
comment 0xF060 ;read config E1 (bit 3), E2 (bit 4), E3 (bit 5) from PCB.
comment 0xF071 ;Test E2 on PCB, normally high
comment 0xF076 ;Test Serial DSR
;----------------------------------------------------------
;FMT Command interperter
;----------------------------------------------------------
box 0xF0F3 0xF121 ;FMT Command Interperter
comment 0xF0F3 ;bitmask command FMT
comment 0xF0F5 ;is command 0x23 (get version number)
comment 0xF0F5 ;if command = 0x23 change it to 0x09
comment 0xF0FB ;is command > 0x30
comment 0xF0FF ;if command > 0x30 subtract 0x22
comment 0xF104 ;B*2 - set pointer correctly for function table
comment 0xF105 ;if command > 0x13 branch to Command_FMT_Invalid
comment 0xF109 ;Command_FunctionTable
;----------------------------------------------------------
box 0xF150 0xF1B0
box 0xF1B1 0xF1E4 ;Serial Data Receive
code 0xF1B1 SerialData_Receive
;----------------------------------------------------------
;Serial Data Transmit
;----------------------------------------------------------
box 0xF1E5 0xF210 ;Serial Data Transmit
code 0xF1E5 SerialData_Transmit
comment 0xF1FE ;Test E3 on PCB, normally high
comment 0xF201 ;skip XON XOFF check
comment 0xF203 ;Check XOFF
comment 0xF20A ;Check XON
;----------------------------------------------------------
;----------------------------------------------------------
;Command_FMT Blocks
;----------------------------------------------------------
box 0xF212 0xF22D ;Command_FMT06_DiskFormat
box 0xF230 0xF364 ;Command_FMT00_CreateDirectory
box 0xF365 0xF422 ;Command_FMT0D_FileNameChange
box 0xF425 0xF493 ;Command_FMT05_FileDelete
box 0xF495 0xF4CF ;Command_FMT02_FileClose
box 0xF4D0 0xF63B ;Command_FMT01_FileOpen
box 0xF63D 0xF69A ;Command_FMT04_File_Write
box 0xF69D 0xF6F1 ;Command_FMT03_FileRead
box 0xF6F3 0xF745 ;Command_FMT07_DriveStatus
box 0xF746 0xF755 ;Command_FMT0C_DriveCondition
box 0xF757 0xF769 ;Command_FMT33_SystemVersionInfo Command_FMT23_DriveVersionInfo
box 0xF76B 0xF78D ;Command_FMT31_DriveMemorySet
box 0xF78E 0xF7C4 ;Command_FMT32_DriveMemoryGet
box 0xF7DC 0xF7FF ;Command_FMT34_ExecuteProgram
box 0xF801 0xF822 ;Command_FMT30_SectorModeReadWrite
;----------------------------------------------------------
code 0xF716 Trap
comment 0xF757 ;LDD A=data bytes, B=return code
comment 0xF75A ;Table_SysInfo
comment 0xF75F ;LDD A=data bytes, B=return code
comment 0xF762 ;Table_Version
;----------------------------------------------------------
;SWI_Funct Blocks
;----------------------------------------------------------
box 0xF824 0xF86F ;SWI_Funct(0x00)
box 0xF870 0xF891 ;SWI_Funct(0x0A)
box 0xF949 0xF996 ;SWI_Funct(0x03)
box 0xF998 0xF9BA ;SWI_Funct(0x02)
box 0xF9BB 0xF9D8 ;SWI_Funct(0x01)
box 0xF9DA 0xFA5F ;SWI_Funct(0x05)
box 0xFA61 0xFAF0 ;SWI_Funct(0x08) SWI_Funct(0x07)
box 0xFAF1 0xFC4E ;SWI_Funct(0x04)
box 0xFC51 0xFDAF ;SWI_Funct(0x0E) SWI_Funct(0x06) SWI_Funct(0x09) SWI_Funct(0x0C) SWI_Funct(0x0D) SWI_Funct(0x14)
box 0xFDB0 0xFE56 ;SWI_Funct(0x15)
box 0xFE9A 0xFEB5 ;SWI_Funct(0x0B)
;----------------------------------------------------------
comment 0xF881 ;Branch Trick, OpCode at F882 is CLR B
comment 0xFA0F ;Table4 Unknown
comment 0xFAB0 ;Table1 Unknown
;----------------------------------------------------------
;packet checksum
;----------------------------------------------------------
box 0xFE59 0xFE99 ;Packet checksum code
code 0xFE59 Checksum_1 ;SWI Call 0x12
comment 0xFE5B ;acc D = 0x0011
code 0xFE60 Checksum_2 ;SWI Call 0x13
comment 0xFE64 ;increment index by 0x13 bytes
comment 0xFE65 ;acc D = 0x0500
code 0xFE68 Checksum_Branch
code 0xFE70 Checksum_Loop
;----------------------------------------------------------
;----------------------------------------------------------
;Clear Data
;----------------------------------------------------------
box 0xFEB6 0xFEBF ;Clear Memory at X for B or D bytes
code 0xFEB6 Clear_X_Size_B ;Clear A and X for B bytes
code 0xFEB7 Clear_X_Size_D ;Clear X for D bytes
;----------------------------------------------------------
;----------------------------------------------------------
;Delay loops
;----------------------------------------------------------
box 0xFEC0 0xFECD ;Delay Loops
code 0xFEC0 DelayLoop02 ;2 loops of 0x99
code 0xFEC3 DelayLoop14 ;14 loops of 0x99
code 0xFEC5 DelayLoop_B ;B loops of 0x99
;----------------------------------------------------------
box 0xFECE 0xFF12
comment 0xFF4F ;Test E1 on PCB, normally high
;----------------------------------------------------------
;Software Interrupt
;----------------------------------------------------------
BOX 0xFF13 0xFF29 ;Software Interrupt
CODE 0xFF13 SWI ;unwind stack from SWI to origianl PC+1
COMMENT 0xFF18 ;pull address of SWI call (PC+1)
COMMENT 0xFF19 ;get byte from SWI PC+1
COMMENT 0xFF1B ;IX++
COMMENT 0xFF1C ;push x to stack (PC of SWI + 2)
COMMENT 0xFF1D ;SWI_LookupTable
COMMENT 0xFF20 ;shift B left (=B*2)
COMMENT 0xFF21 ;add B to X
COMMENT 0xFF22 ;load data at X to IX
COMMENT 0xFF24 ;push X to stack
COMMENT 0xFF25 ;jump down and get original B from SWI stack dump
COMMENT 0xFF29 ;Return, jumps to function from table
;----------------------------------------------------------
;----------------------------------------------------------
;IRQ1, IRQ2 Handeling
;----------------------------------------------------------
BOX 0xFF2A 0xFF5E ;hardware interrupt handeling
CODE 0xFF2A IRQ2TOI
CODE 0xFF5E IRQ1,IQR2
;----------------------------------------------------------