From 329b80677497c38042fb219f3ab25066918c9bf1 Mon Sep 17 00:00:00 2001 From: Alexander Fedotov Date: Fri, 19 Jun 2020 17:00:29 +0300 Subject: [PATCH] Initial Cortex R-profile support. --- CMSIS/Core_R/Include/cmsis_compiler.h | 283 ++++ CMSIS/Core_R/Include/cmsis_cp15.h | 1255 +++++++++++++++++ CMSIS/Core_R/Include/cmsis_gcc.h | 543 +++++++ CMSIS/Core_R/Include/cmsis_version.h | 39 + CMSIS/Core_R/Include/core_cr52.h | 387 +++++ Device/ARM/ARMCR52/Include/ARMCR52.h | 105 ++ .../ARM/ARMCR52/Include/ARMCR52_DSP_DP_FP.h | 105 ++ Device/ARM/ARMCR52/Include/ARMCR52_FP.h | 105 ++ Device/ARM/ARMCR52/Include/system_ARMCR52.h | 57 + Device/ARM/ARMCR52/Source/GCC/gcc_arm.ld | 371 +++++ .../ARM/ARMCR52/Source/GCC/startup_ARMCR52.c | 158 +++ Device/ARM/ARMCR52/Source/system_ARMCR52.c | 109 ++ Device/ARM/ARMCR52/Source/tcm_init.c | 66 + 13 files changed, 3583 insertions(+) create mode 100644 CMSIS/Core_R/Include/cmsis_compiler.h create mode 100644 CMSIS/Core_R/Include/cmsis_cp15.h create mode 100644 CMSIS/Core_R/Include/cmsis_gcc.h create mode 100644 CMSIS/Core_R/Include/cmsis_version.h create mode 100644 CMSIS/Core_R/Include/core_cr52.h create mode 100644 Device/ARM/ARMCR52/Include/ARMCR52.h create mode 100644 Device/ARM/ARMCR52/Include/ARMCR52_DSP_DP_FP.h create mode 100644 Device/ARM/ARMCR52/Include/ARMCR52_FP.h create mode 100644 Device/ARM/ARMCR52/Include/system_ARMCR52.h create mode 100644 Device/ARM/ARMCR52/Source/GCC/gcc_arm.ld create mode 100644 Device/ARM/ARMCR52/Source/GCC/startup_ARMCR52.c create mode 100644 Device/ARM/ARMCR52/Source/system_ARMCR52.c create mode 100644 Device/ARM/ARMCR52/Source/tcm_init.c diff --git a/CMSIS/Core_R/Include/cmsis_compiler.h b/CMSIS/Core_R/Include/cmsis_compiler.h new file mode 100644 index 0000000000..a80c867e59 --- /dev/null +++ b/CMSIS/Core_R/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/CMSIS/Core_R/Include/cmsis_cp15.h b/CMSIS/Core_R/Include/cmsis_cp15.h new file mode 100644 index 0000000000..02f9e2d11f --- /dev/null +++ b/CMSIS/Core_R/Include/cmsis_cp15.h @@ -0,0 +1,1255 @@ +/**************************************************************************//** + * @file cmsis_cp15.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_CP15_H +#define __CMSIS_CP15_H + +/** \brief Get MIDR + This function returns the value of the Main ID Register. + \return Main ID Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MIDR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 0); + return result; +} + +/** \brief Get CTR + This function returns the value of the Cache Type Register. + \return Cache Type Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CTR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 1); + return result; +} + +/** \brief Get TCMTR + This function returns the value of the TCM Type Register. + \return TCM Type Register value + */ +__STATIC_FORCEINLINE uint32_t __get_TCMTR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 2); + return result; +} + +/** \brief Get TLBTR + This function returns the value of the TLB Type Register. + \return TLB Type Register value + */ +__STATIC_FORCEINLINE uint32_t __get_TLBTR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 3); + return result; +} + +/** \brief Get MPUIR + This function returns the value of the MPU Type Register. + \return MPU Type Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MPUIR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 4); + return result; +} + +/** \brief Get MPIDR + This function returns the value of the Multiprocessor Affinity Register. + \return Multiprocessor Affinity Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MPIDR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 5); + return result; +} + +/** \brief Get REVIDR + This function returns the value of the Revision ID Register. + \return Revision ID Register value + */ +__STATIC_FORCEINLINE uint32_t __get_REVIDR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 6); + return result; +} + +/** \brief Get MIDR alias + This function returns the value of the Alias of the Main ID Register,. + \return Alias of the Main ID Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MIDR_alias(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 0, 7); + return result; +} + +/** \brief Get ID_PFR0 + This function returns the value of the Processor Feature Register 0. + \return Processor Feature Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_ID_PFR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 1, 0); + return result; +} + +/** \brief Get ID_PFR1 + This function returns the value of the Processor Feature Register 1. + \return Processor Feature Register 1 value + */ +__STATIC_FORCEINLINE uint32_t __get_ID_PFR1(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 1, 1); + return result; +} + +/** \brief Get ID_DFR0 + This function returns the value of the Debug Feature Register 0. + \return Debug Feature Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_ID_DFR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 1, 2); + return result; +} + +/** \brief Get ID_AFR0 + This function returns the value of the Auxiliary Feature Register 0. + \return Auxiliary Feature Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_ID_AFR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 1, 3); + return result; +} + +/** \brief Get ID_MMFR0 + This function returns the value of the Memory Model Feature Register 0. + \return Memory Model Feature Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_ID_MMFR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 1, 4); + return result; +} + +/** \brief Get ID_MMFR1 + This function returns the value of the Memory Model Feature Register 1. + \return Memory Model Feature Register 1 value + */ +__STATIC_FORCEINLINE uint32_t __get_ID_MMFR1(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 1, 5); + return result; +} + +/** \brief Get ID_MMFR2 + This function returns the value of the Memory Model Feature Register 2. + \return Memory Model Feature Register 2 value + */ +__STATIC_FORCEINLINE uint32_t __get_ID_MMFR2(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 1, 6); + return result; +} + +/** \brief Get ID_MMFR3 + This function returns the value of the Memory Model Feature Register 3. + \return Memory Model Feature Register 3 value + */ +__STATIC_FORCEINLINE uint32_t __get_ID_MMFR3(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 1, 7); + return result; +} + +/** \brief Get ID_ISAR0 + This function returns the value of the Instruction Set Attribute Register 0. + \return Instruction Set Attribute Register 0 value + */ +__STATIC_FORCEINLINE uint32_t __get_ID_ISAR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 2, 0); + return result; +} + +/** \brief Get ID_ISAR1 + This function returns the value of the Instruction Set Attribute Register 1. + \return Instruction Set Attribute Register 1 value + */ +__STATIC_FORCEINLINE uint32_t __get_ID_ISAR1(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 2, 1); + return result; +} + +/** \brief Get ID_ISAR2 + This function returns the value of the Instruction Set Attribute Register 2. + \return Instruction Set Attribute Register 2 value + */ +__STATIC_FORCEINLINE uint32_t __get_ID_ISAR2(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 2, 2); + return result; +} + +/** \brief Get ID_ISAR3 + This function returns the value of the Instruction Set Attribute Register 3. + \return Instruction Set Attribute Register 3 value + */ +__STATIC_FORCEINLINE uint32_t __get_ID_ISAR3(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 2, 3); + return result; +} + +/** \brief Get ID_ISAR4 + This function returns the value of the Instruction Set Attribute Register 4. + \return Instruction Set Attribute Register 4 value + */ +__STATIC_FORCEINLINE uint32_t __get_ID_ISAR4(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 2, 4); + return result; +} + +/** \brief Get ID_ISAR5 + This function returns the value of the Instruction Set Attribute Register 5. + \return Instruction Set Attribute Register 5 value + */ +__STATIC_FORCEINLINE uint32_t __get_ID_ISAR5(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 2, 5); + return result; +} + +/** \brief Get ID_MMFR4 + This function returns the value of the Memory Model Feature Register 4. + \return Memory Model Feature Register 4 value + */ +__STATIC_FORCEINLINE uint32_t __get_ID_MMFR4(void) +{ + uint32_t result; + __get_CP(15, 0, result, 0, 2, 6); + return result; +} + +/** \brief Get SCTLR + This function returns the value of the System Control Register. + \return System Control Register + */ +__STATIC_FORCEINLINE uint32_t __get_SCTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 0, 0); + return result; +} + +/** \brief Set SCTLR + This function assigns the given value to the System Control Register. + \param [in] sctlr System Control Register value to set + */ +__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr) +{ + __set_CP(15, 0, sctlr, 1, 0, 0); +} + +/** \brief Get NSACR + This function returns the value of the Non-Secure Access Control Register. + \return Non-Secure Access Control Register + */ +__STATIC_FORCEINLINE uint32_t __get_NSACR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 1, 1, 2); + return result; +} + +/** \brief Get DFAR + This function returns the value of the Data Fault Address Register. + \return Data Fault Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_DFAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 6, 0, 0); + return result; +} + +/** \brief Set DFAR + This function assigns the given value to the Data Fault Address Register. + \param [in] dfar Data Fault Address Register value to set + */ +__STATIC_FORCEINLINE void __set_DFAR(uint32_t dfar) +{ + __set_CP(15, 0, dfar, 6, 0, 0); +} + +/** \brief Get IFAR + This function returns the value of the Instruction Fault Address Register. + \return Instruction Fault Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_IFAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 6, 0, 2); + return result; +} + +/** \brief Set IFAR + This function assigns the given value to the Instruction Fault Address Register. + \param [in] ifar Instruction Fault Address Register value to set + */ +__STATIC_FORCEINLINE void __set_IFAR(uint32_t ifar) +{ + __set_CP(15, 0, ifar, 6, 0, 2); +} + +/** \brief Get PRSELR + This function returns the value of the Protection Region Selection Register. + \return Protection Region Selection Register + */ +__STATIC_FORCEINLINE uint32_t __get_PRSELR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 6, 2, 1); + return result; +} + +/** \brief Set PRSELR + This function assigns the given value to the Protection Region Selection Register. + \param [in] prselr Protection Region Selection Register value to set + */ +__STATIC_FORCEINLINE void __set_PRSELR(uint32_t prselr) +{ + __set_CP(15, 0, prselr, 6, 2, 1); +} + +/** \brief Get PRBAR + This function returns the value of the Protection Region Base Address Register. + \return Protection Region Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_PRBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 6, 3, 0); + return result; +} + +/** \brief Set PRBAR + This function assigns the given value to the Protection Region Base Address Register. + \param [in] prbar Protection Region Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_PRBAR(uint32_t prbar) +{ + __set_CP(15, 0, prbar, 6, 3, 0); +} + +/** \brief Get PRLAR + This function returns the value of the Protection Region Limit Address Register. + \return Protection Region Limit Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_PRLAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 6, 3, 1); + return result; +} + +/** \brief Set PRLAR + This function assigns the given value to the Protection Region Limit Address Register. + \param [in] prlar Protection Region Limit Address Register value to set + */ +__STATIC_FORCEINLINE void __set_PRLAR(uint32_t prlar) +{ + __set_CP(15, 0, prlar, 6, 3, 1); +} + +/** \brief Get PAR + This function returns the value of the Physical Address Register. + \return Physical Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_PAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 7, 4, 0); + return result; +} + +/** \brief Set PAR + This function assigns the given value to the Physical Address Register. + \param [in] par PPhysical Address Register value to set + */ +__STATIC_FORCEINLINE void __set_PAR(uint32_t par) +{ + __set_CP(15, 0, par, 7, 4, 0); +} + +/** \brief Get IMP_ATCMREGIONR + This function returns the value of the TCM Region Register A. + \return TCM Region Register A + */ +__STATIC_FORCEINLINE uint32_t __get_IMP_ATCMREGIONR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 1, 0); + return result; +} + +/** \brief Set IMP_ATCMREGIONR + This function assigns the given value to the TCM Region Register A. + \param [in] config TCM Region Register A value to set + */ +__STATIC_FORCEINLINE void __set_IMP_ATCMREGIONR(uint32_t config) +{ + __set_CP(15, 0, config, 9, 1, 0); +} + +/** \brief Get IMP_BTCMREGIONR + This function returns the value of the TCM Region Register B. + \return TCM Region Register B + */ +__STATIC_FORCEINLINE uint32_t __get_IMP_BTCMREGIONR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 1, 1); + return result; +} + +/** \brief Set IMP_BTCMREGIONR + This function assigns the given value to the TCM Region Register B. + \param [in] config TCM Region Register B value to set + */ +__STATIC_FORCEINLINE void __set_IMP_BTCMREGIONR(uint32_t config) +{ + __set_CP(15, 0, config, 9, 1, 1); +} + +/** \brief Get IMP_CTCMREGIONR + This function returns the value of the TCM Region Register C. + \return TCM Region Register C + */ +__STATIC_FORCEINLINE uint32_t __get_IMP_CTCMREGIONR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 1, 2); + return result; +} + +/** \brief Set IMP_CTCMREGIONR + This function assigns the given value to the TCM Region Register C. + \param [in] config TCM Region Register C value to set + */ +__STATIC_FORCEINLINE void __set_IMP_CTCMREGIONR(uint32_t config) +{ + __set_CP(15, 0, config, 9, 1, 2); +} + +/** \brief Get PMCR + This function returns the value of the Performance Monitors Control Register. + \return Performance Monitors Control Register + */ +__STATIC_FORCEINLINE uint32_t __get_PMCR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 12, 0); + return result; +} + +/** \brief Set PMCR + This function assigns the given value to the Performance Monitors Control Register. + \param [in] pmcr Performance Monitors Control Register value to set + */ +__STATIC_FORCEINLINE void __set_PMCR(uint32_t pmcr) +{ + __set_CP(15, 0, pmcr, 9, 12, 0); +} + +/** \brief Get PMCNTENSET + This function returns the value of the Performance Monitors Count Enable Set Register. + \return Performance Monitors Count Enable Set Register + */ +__STATIC_FORCEINLINE uint32_t __get_PMCNTENSET(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 12, 1); + return result; +} + +/** \brief Set PMCNTENSET + This function assigns the given value to the Performance Monitors Count Enable Set Register. + \param [in] pmcntenset Performance Monitors Count Enable Set Register value to set + */ +__STATIC_FORCEINLINE void __set_PMCNTENSET(uint32_t pmcntenset) +{ + __set_CP(15, 0, pmcntenset, 9, 12, 1); +} + +/** \brief Get PMCNTENCLR + This function returns the value of the Performance Monitors Count Enable Clear Register. + \return Performance Monitors Count Enable Clear Register + */ +__STATIC_FORCEINLINE uint32_t __get_PMCNTENCLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 12, 2); + return result; +} + +/** \brief Set PMCNTENCLR + This function assigns the given value to the Performance Monitors Count Enable Clear Register. + \param [in] pmcntenclr Performance Monitors Count Enable Clear Register value to set + */ +__STATIC_FORCEINLINE void __set_PMCNTENCLR(uint32_t pmcntenclr) +{ + __set_CP(15, 0, pmcntenclr, 9, 12, 2); +} + +/** \brief Get PMOVSR + This function returns the value of the Performance Monitor Overflow Flag Status Clear Register. + \return Performance Monitor Overflow Flag Status Clear Register + */ +__STATIC_FORCEINLINE uint32_t __get_PMOVSR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 12, 3); + return result; +} + +/** \brief Set PMOVSR + This function assigns the given value to the Performance Monitor Overflow Flag Status Clear Register. + \param [in] pmovsr Performance Monitor Overflow Flag Status Clear Register value to set + */ +__STATIC_FORCEINLINE void __set_PMOVSR(uint32_t pmovsr) +{ + __set_CP(15, 0, pmovsr, 9, 12, 3); +} + +/** \brief Set PMSWINC + This function assigns the given value to the Performance Monitors Software Increment Register. + \param [in] pmswinc Performance Monitors Software Increment Register value to set + */ +__STATIC_FORCEINLINE void __set_PMSWINC(uint32_t pmswinc) +{ + __set_CP(15, 0, pmswinc, 9, 12, 4); +} + +/** \brief Get PMSELR + This function returns the value of the Performance Monitors Event Counter Selection Register. + \return Performance Monitors Event Counter Selection Register + */ +__STATIC_FORCEINLINE uint32_t __get_PMSELR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 12, 5); + return result; +} + +/** \brief Set PMSELR + This function assigns the given value to the Performance Monitors Event Counter Selection Register. + \param [in] pmselr Performance Monitors Event Counter Selection Register value to set + */ +__STATIC_FORCEINLINE void __set_PMSELR(uint32_t pmselr) +{ + __set_CP(15, 0, pmselr, 9, 12, 5); +} + +/** \brief Get PMCEID0 + This function returns the value of the Performance Monitors Common Event Identification Register 0. + \return Performance Monitors Common Event Identification Register 0 + */ +__STATIC_FORCEINLINE uint32_t __get_PMCEID0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 12, 6); + return result; +} + +/** \brief Get PMCEID1 + This function returns the value of the Performance Monitors Common Event Identification Register 1. + \return Performance Monitors Common Event Identification Register 1 + */ +__STATIC_FORCEINLINE uint32_t __get_PMCEID1(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 12, 7); + return result; +} + +/** \brief Get PMCCNTR + This function returns the value of the Performance Monitors Cycle Count Register. + \return Performance Monitors Cycle Count Register + */ +__STATIC_FORCEINLINE uint32_t __get_PMCCNTR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 13, 0); + return result; +} + +/** \brief Set PMCCNTR + This function assigns the given value to the Performance Monitors Cycle Count Register. + \param [in] pmccntr Performance Monitors Cycle Count Register value to set + */ +__STATIC_FORCEINLINE void __set_PMCCNTR(uint32_t pmccntr) +{ + __set_CP(15, 0, pmccntr, 9, 13, 0); +} + +/** \brief Get PMXEVTYPER + This function returns the value of the Performance Monitors Selected Event Type Register. + \return Performance Monitors Selected Event Type Register + */ +__STATIC_FORCEINLINE uint32_t __get_PMXEVTYPER(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 13, 1); + return result; +} + +/** \brief Set PMXEVTYPER + This function assigns the given value to the Performance Monitors Selected Event Type Register. + \param [in] pmxevtyper Performance Monitors Selected Event Type Register value to set + */ +__STATIC_FORCEINLINE void __set_PMXEVTYPER(uint32_t pmxevtyper) +{ + __set_CP(15, 0, pmxevtyper, 9, 13, 1); +} + +/** \brief Get PMXEVCNTR + This function returns the value of the Performance Monitors Selected Event Count Register. + \return Performance Monitors Selected Event Count Register + */ +__STATIC_FORCEINLINE uint32_t __get_PMXEVCNTR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 13, 2); + return result; +} + +/** \brief Set PMXEVCNTR + This function assigns the given value to the Performance Monitors Selected Event Count Register. + \param [in] pmxevcntr Performance Monitors Selected Event Count Register value to set + */ +__STATIC_FORCEINLINE void __set_PMXEVCNTR(uint32_t pmxevcntr) +{ + __set_CP(15, 0, pmxevcntr, 9, 13, 2); +} + +/** \brief Get PMUSERENR + This function returns the value of the Performance Monitors User Enable Register. + \return Performance Monitors User Enable Register + */ +__STATIC_FORCEINLINE uint32_t __get_PMUSERENR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 14, 0); + return result; +} + +/** \brief Set PMUSERENR + This function assigns the given value to the Performance Monitors User Enable Register. + \param [in] pmuserenr Performance Monitors User Enable Register value to set + */ +__STATIC_FORCEINLINE void __set_PMUSERENR(uint32_t pmuserenr) +{ + __set_CP(15, 0, pmuserenr, 9, 14, 0); +} + +/** \brief Get PMINTENSET + This function returns the value of the Performance Monitors Interrupt Enable Set Register. + \return Performance Monitors Interrupt Enable Set Register + */ +__STATIC_FORCEINLINE uint32_t __get_PMINTENSET(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 14, 1); + return result; +} + +/** \brief Set PMINTENSET + This function assigns the given value to the Performance Monitors Interrupt Enable Set Register. + \param [in] pmintenset Performance Monitors Interrupt Enable Set Register value to set + */ +__STATIC_FORCEINLINE void __set_PMINTENSET(uint32_t pmintenset) +{ + __set_CP(15, 0, pmintenset, 9, 14, 1); +} + +/** \brief Get PMINTENCLR + This function returns the value of the Performance Monitors Interrupt Enable Clear Register. + \return Performance Monitors Interrupt Enable Clear Register + */ +__STATIC_FORCEINLINE uint32_t __get_PMINTENCLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 14, 2); + return result; +} + +/** \brief Set PMINTENCLR + This function assigns the given value to the Performance Monitors Interrupt Enable Clear Register. + \param [in] pmintenclr Performance Monitors Interrupt Enable Clear Register value to set + */ +__STATIC_FORCEINLINE void __set_PMINTENCLR(uint32_t pmintenclr) +{ + __set_CP(15, 0, pmintenclr, 9, 14, 2); +} + +/** \brief Get PMOVSSET + This function returns the value of the Performance Monitor Overflow Flag Status Set Register. + \return Performance Monitor Overflow Flag Status Set Register + */ +__STATIC_FORCEINLINE uint32_t __get_PMOVSSET(void) +{ + uint32_t result; + __get_CP(15, 0, result, 9, 14, 3); + return result; +} + +/** \brief Set PMOVSSET + This function assigns the given value to the Performance Monitor Overflow Flag Status Set Register. + \param [in] pmovsset Performance Monitor Overflow Flag Status Set Register value to set + */ +__STATIC_FORCEINLINE void __set_PMOVSSET(uint32_t pmovsset) +{ + __set_CP(15, 0, pmovsset, 9, 14, 3); +} + +/** \brief Get MAIR0 + This function returns the value of the Memory Attribute Indirection Registers 0. + \return Memory Attribute Indirection Registers 0 + */ +__STATIC_FORCEINLINE uint32_t __get_MAIR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 10, 2, 0); + return result; +} + +/** \brief Set MAIR0 + This function assigns the given value to the Memory Attribute Indirection Registers 0. + \param [in] mair0 Memory Attribute Indirection Registers 0 value to set + */ +__STATIC_FORCEINLINE void __set_MAIR0(uint32_t mair0) +{ + __set_CP(15, 0, mair0, 10, 2, 0); +} + +/** \brief Get MAIR1 + This function returns the value of the Memory Attribute Indirection Registers 1. + \return Memory Attribute Indirection Registers 1 + */ +__STATIC_FORCEINLINE uint32_t __get_MAIR1(void) +{ + uint32_t result; + __get_CP(15, 0, result, 10, 2, 1); + return result; +} + +/** \brief Set MAIR0 + This function assigns the given value to the Memory Attribute Indirection Registers 1. + \param [in] mair1 Memory Attribute Indirection Registers 1 value to set + */ +__STATIC_FORCEINLINE void __set_MAIR1(uint32_t mair1) +{ + __set_CP(15, 0, mair1, 10, 2, 1); +} + +/** \brief Get AMAIR0 + This function returns the value of the Auxiliary Memory Attribute Indirection Register 0. + \return Auxiliary Memory Attribute Indirection Register 0 + */ +__STATIC_FORCEINLINE uint32_t __get_AMAIR0(void) +{ + uint32_t result; + __get_CP(15, 0, result, 10, 3, 0); + return result; +} + +/** \brief Set AMAIR0 + This function assigns the given value to the Auxiliary Memory Attribute Indirection Register 0. + \param [in] config Auxiliary Memory Attribute Indirection Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_AMAIR0(uint32_t config) +{ + __set_CP(15, 0, config, 10, 3, 0); +} + +/** \brief Get AMAIR1 + This function returns the value of the Auxiliary Memory Attribute Indirection Register 1. + \return Auxiliary Memory Attribute Indirection Register 1 + */ +__STATIC_FORCEINLINE uint32_t __get_AMAIR1(void) +{ + uint32_t result; + __get_CP(15, 0, result, 10, 3, 1); + return result; +} + +/** \brief Set AMAIR1 + This function assigns the given value to the Auxiliary Memory Attribute Indirection Register 1. + \param [in] config Auxiliary Memory Attribute Indirection Register 1 value to set + */ +__STATIC_FORCEINLINE void __set_AMAIR1(uint32_t config) +{ + __set_CP(15, 0, config, 10, 3, 1); +} + +/** \brief Get IMP_SLAVEPCTLR + This function returns the value of the Slave Port Control Register. + \return Slave Port Control Register + */ +__STATIC_FORCEINLINE uint32_t __get_IMP_SLAVEPCTLR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 11, 0, 0); + return result; +} + +/** \brief Set IMP_SLAVEPCTLR + This function assigns the given value to the Slave Port Control Register. + \param [in] slavepctlr Slave Port Control Register value to set + */ +__STATIC_FORCEINLINE void __set_IMP_SLAVEPCTLR(uint32_t slavepctlr) +{ + __set_CP(15, 0, slavepctlr, 11, 0, 0); +} + +/** \brief Get VBAR + This function returns the value of the Vector Base Address Register. + \return Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_VBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 0); + return result; +} + +/** \brief Set VBAR + This function assigns the given value to the Vector Base Address Register. + \param [in] vbar Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar) +{ + __set_CP(15, 0, vbar, 12, 0, 0); +} + +/** \brief Get RVBAR + This function returns the value of the Reset Vector Base Address Register. + \return Reset Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_RVBAR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 0, 1); + return result; +} + +/** \brief Get ISR + This function returns the value of the Interrupt Status Register. + \return Interrupt Status Register + */ +__STATIC_FORCEINLINE uint32_t __get_ISR(void) +{ + uint32_t result; + __get_CP(15, 0, result, 12, 1, 0); + return result; +} + +/** \brief Get CCSIDR + This function returns the value of the Current Cache Size ID Register. + \return Current Cache Size ID Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void) +{ + uint32_t result; + __get_CP(15, 1, result, 0, 0, 0); + return result; +} + +/** \brief Get CLIDR + This function returns the value of the Cache Level ID Register. + \return Cache Level ID Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CLIDR(void) +{ + uint32_t result; + __get_CP(15, 1, result, 0, 0, 1); + return result; +} + +/** \brief Get AIDR + This function returns the value of the Auxiliary ID Register. + \return Auxiliary ID Register value + */ +__STATIC_FORCEINLINE uint32_t __get_AIDR(void) +{ + uint32_t result; + __get_CP(15, 1, result, 0, 0, 7); + return result; +} + +/** \brief Get IMP_CSCTLR + This function returns the value of the Cache Segregation Control Register. + \return Cache Segregation Control Register + */ +__STATIC_FORCEINLINE uint32_t __get_IMP_CSCTLR(void) +{ + uint32_t result; + __get_CP(15, 1, result, 9, 1, 0); + return result; +} + +/** \brief Set IMP_CSCTLR + This function assigns the given value to the Cache Segregation Control Register. + \param [in] csctlr Cache Segregation Control Register value to set + */ +__STATIC_FORCEINLINE void __set_IMP_CSCTLR(uint32_t csctlr) +{ + __set_CP(15, 1, csctlr, 9, 1, 0); +} + +/** \brief Get IMP_BPCTLR + This function returns the value of the Branch Predictor Control Register. + \return Branch Predictor Control Register + */ +__STATIC_FORCEINLINE uint32_t __get_IMP_BPCTLR(void) +{ + uint32_t result; + __get_CP(15, 1, result, 9, 1, 1); + return result; +} + +/** \brief Set IMP_BPCTLR + This function assigns the given value to the Branch Predictor Control Register. + \param [in] bpctlr Branch Predictor Control Register value to set + */ +__STATIC_FORCEINLINE void __set_IMP_BPCTLR(uint32_t bpctlr) +{ + __set_CP(15, 1, bpctlr, 9, 1, 1); +} + +/** \brief Get IMP_MEMPROTCLR + This function returns the value of the Memory Protection Control Register. + \return Memory Protection Control Register + */ +__STATIC_FORCEINLINE uint32_t __get_IMP_MEMPROTCLR(void) +{ + uint32_t result; + __get_CP(15, 1, result, 9, 1, 2); + return result; +} + +/** \brief Set IMP_MEMPROTCLR + This function assigns the given value to the Memory Protection Control Register. + \param [in] memprotclr Memory Protection Control Register value to set + */ +__STATIC_FORCEINLINE void __set_IMP_MEMPROTCLR(uint32_t memprotclr) +{ + __set_CP(15, 1, memprotclr, 9, 1, 2); +} + +/** \brief Get CSSELR + This function returns the value of the Cache Size Selection Register. + \return Cache Size Selection Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CSSELR(void) +{ + uint32_t result; + __get_CP(15, 2, result, 0, 0, 7); + return result; +} + +/** \brief Get HSCTLR + This function returns the value of the Hyp System Control Register. + \return Hyp System Control Register + */ +__STATIC_FORCEINLINE uint32_t __get_HSCTLR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 1, 0, 0); + return result; +} + +/** \brief Set HSCTLR + This function assigns the given value to the Hyp System Control Register. + \param [in] hsctlr Hyp System Control Register value to set + */ +__STATIC_FORCEINLINE void __set_HSCTLR(uint32_t hsctlr) +{ + __set_CP(15, 4, hsctlr, 1, 0, 0); +} + +/** \brief Get HACTLR + This function returns the value of the Hyp Auxiliary Control Register. + \return Hyp Auxiliary Control Register + */ +__STATIC_FORCEINLINE uint32_t __get_HACTLR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 1, 0, 1); + return result; +} + +/** \brief Set HACTLR + This function assigns the given value to the Hyp Auxiliary Control Register. + \param [in] hactlr Hyp Auxiliary Control Register value to set + */ +__STATIC_FORCEINLINE void __set_HACTLR(uint32_t hactlr) +{ + __set_CP(15, 4, hactlr, 1, 0, 1); +} + +/** \brief Get HACTLR2 + This function returns the value of the Hyp Auxiliary Control Register 2. + \return Hyp Auxiliary Control Register 2 + */ +__STATIC_FORCEINLINE uint32_t __get_HACTLR2(void) +{ + uint32_t result; + __get_CP(15, 4, result, 1, 0, 3); + return result; +} + +/** \brief Set HACTLR2 + This function assigns the given value to the Hyp Auxiliary Control Register 2. + \param [in] hactlr Hyp Auxiliary Control Register 2 value to set + */ +__STATIC_FORCEINLINE void __set_HACTLR2(uint32_t hactlr2) +{ + __set_CP(15, 4, hactlr2, 1, 0, 3); +} + +/** \brief Get HPRSELR + This function returns the value of the Hyp Protection Region Selection Register. + \return Hyp Protection Region Selection Register + */ +__STATIC_FORCEINLINE uint32_t __get_HPRSELR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 6, 2, 1); + return result; +} + +/** \brief Set HPRSELR + This function assigns the given value to the Hyp Protection Region Selection Register. + \param [in] hprselr Hyp Protection Region Selection Register value to set + */ +__STATIC_FORCEINLINE void __set_HPRSELR(uint32_t hprselr) +{ + __set_CP(15, 4, hprselr, 6, 2, 1); +} + +/** \brief Get HPRBAR + This function returns the value of the Hyp Protection Region Base Address Register. + \return Hyp Protection Region Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_HPRBAR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 6, 3, 0); + return result; +} + +/** \brief Set HPRBAR + This function assigns the given value to the Hyp Protection Region Base Address Register. + \param [in] hprbar Hyp Protection Region Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_HPRBAR(uint32_t hprbar) +{ + __set_CP(15, 4, hprbar, 6, 3, 0); +} + +/** \brief Get HPRLAR + This function returns the value of the Hyp Protection Region Limit Address Register. + \return Hyp Protection Region Limit Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_HPRLAR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 6, 3, 1); + return result; +} + +/** \brief Set HPRLAR + This function assigns the given value to the Hyp Protection Region Limit Address Register. + \param [in] hprlar Hyp Protection Region Limit Address Register value to set + */ +__STATIC_FORCEINLINE void __set_HPRLAR(uint32_t hprlar) +{ + __set_CP(15, 4, hprlar, 6, 3, 1); +} + +/** \brief Get HMAIR0 + This function returns the value of the Hyp Memory Attribute Indirection Register 0. + \return Hyp Memory Attribute Indirection Register 0 + */ +__STATIC_FORCEINLINE uint32_t __get_HMAIR0(void) +{ + uint32_t result; + __get_CP(15, 4, result, 10, 2, 0); + return result; +} + +/** \brief Set HMAIR0 + This function assigns the given value to the Hyp Memory Attribute Indirection Register 0. + \param [in] hmair0 Hyp Memory Attribute Indirection Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_HMAIR0(uint32_t hmair0) +{ + __set_CP(15, 4, hmair0, 10, 2, 0); +} + +/** \brief Get HMAIR1 + This function returns the value of the Hyp Memory Attribute Indirection Register 1. + \return Hyp Memory Attribute Indirection Register 1 + */ +__STATIC_FORCEINLINE uint32_t __get_HMAIR1(void) +{ + uint32_t result; + __get_CP(15, 4, result, 10, 2, 1); + return result; +} + +/** \brief Set HMAIR1 + This function assigns the given value to the Hyp Memory Attribute Indirection Register 1. + \param [in] hmair1 Hyp Memory Attribute Indirection Register 1 value to set + */ +__STATIC_FORCEINLINE void __set_HMAIR1(uint32_t hmair1) +{ + __set_CP(15, 4, hmair1, 10, 2, 1); +} + +/** \brief Get HAMAIR0 + This function returns the value of the Hyp Auxiliary Memory Attribute Indirection Register 0. + \return Hyp Auxiliary Memory Attribute Indirection Register 0 + */ +__STATIC_FORCEINLINE uint32_t __get_HAMAIR0(void) +{ + uint32_t result; + __get_CP(15, 4, result, 10, 3, 0); + return result; +} + +/** \brief Set HAMAIR0 + This function assigns the given value to the Hyp Auxiliary Memory Attribute Indirection Register 0. + \param [in] hamair0 Hyp Auxiliary Memory Attribute Indirection Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_HAMAIR0(uint32_t hamair0) +{ + __set_CP(15, 4, hamair0, 10, 3, 0); +} + +/** \brief Get HAMAIR1 + This function returns the value of the Hyp Auxiliary Memory Attribute Indirection Register 1. + \return Hyp Auxiliary Memory Attribute Indirection Register 1 + */ +__STATIC_FORCEINLINE uint32_t __get_HAMAIR1(void) +{ + uint32_t result; + __get_CP(15, 4, result, 10, 3, 1); + return result; +} + +/** \brief Set HAMAIR0 + This function assigns the given value to the Hyp Auxiliary Memory Attribute Indirection Register 1. + \param [in] hamair1 Hyp Auxiliary Memory Attribute Indirection Register 1 value to set + */ +__STATIC_FORCEINLINE void __set_HAMAIR1(uint32_t hamair1) +{ + __set_CP(15, 4, hamair1, 10, 3, 1); +} + +/** \brief Get HVBAR + This function returns the value of the Hyp Vector Base Address Register. + \return Hyp Vector Base Address Register + */ +__STATIC_FORCEINLINE uint32_t __get_HVBAR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 12, 0, 0); + return result; +} + +/** \brief Set HVBAR + This function assigns the given value to the Hyp Vector Base Address Register. + \param [in] hvbar Hyp Vector Base Address Register value to set + */ +__STATIC_FORCEINLINE void __set_HVBAR(uint32_t hvbar) +{ + __set_CP(15, 4, hvbar, 12, 0, 0); +} + +/** \brief Get HRMR + This function returns the value of the Hypervisor Reset Management Register. + \return Hypervisor Reset Management Register + */ +__STATIC_FORCEINLINE uint32_t __get_HRMR(void) +{ + uint32_t result; + __get_CP(15, 4, result, 12, 0, 2); + return result; +} + +/** \brief Set HRMR + This function assigns the given value to the Hypervisor Reset Management Register. + \param [in] hrmr Hypervisor Reset Management Register value to set + */ +__STATIC_FORCEINLINE void __set_HRMR(uint32_t hrmr) +{ + __set_CP(15, 4, hrmr, 12, 0, 2); +} + +#endif diff --git a/CMSIS/Core_R/Include/cmsis_gcc.h b/CMSIS/Core_R/Include/cmsis_gcc.h new file mode 100644 index 0000000000..ba20665286 --- /dev/null +++ b/CMSIS/Core_R/Include/cmsis_gcc.h @@ -0,0 +1,543 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __NAKED + #define __NAKED __attribute__((naked)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __EARLY_INIT + /** + \brief Early system init: ECC, TCM etc. + \details This default implementation initializes ECC memory sections + relying on .ecc.table properly in the used linker script. + + */ +__STATIC_FORCEINLINE void __cmsis_cpu_init(void) +{ +#if defined (__ECC_PRESENT) && (__ECC_PRESENT == 1U) + typedef struct { + uint64_t* dest; + uint64_t wlen; + } __ecc_table_t; + + extern const __ecc_table_t __ecc_table_start__; + extern const __ecc_table_t __ecc_table_end__; + + for (__ecc_table_t const* pTable = &__ecc_table_start__; pTable < &__ecc_table_end__; ++pTable) { + for(uint64_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0xDEADBEEFFEEDCAFEUL; + } + } +#endif +} + +#define __EARLY_INIT __cmsis_cpu_init +#endif + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __EL2StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __EL2StackLimit +#endif + +#ifndef __VECTOR_TABLE_EL2 +#define __VECTOR_TABLE_EL2 __EL2_Vectors +#endif + +#ifndef __VECTOR_TABLE_EL1 +#define __VECTOR_TABLE_EL1 __EL1_Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((naked, aligned(32), used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + +/** + \brief Return from Hypervisor exception + \details Return from Hypervisor exception. + */ +#define __ERET() __ASM volatile ("eret") + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + +/** \brief Get ELR Hypervisor Register + \return ELR Hypervisor Register value + */ +__STATIC_FORCEINLINE uint32_t __get_ELR_Hyp(void) +{ + uint32_t result; + __ASM volatile("MRS %0, elr_hyp" : "=r" (result) ); + return(result); +} + +/** \brief Set ELR Hypervisor Register + \param [in] elr_hyp ELR value to set + */ +__STATIC_FORCEINLINE void __set_ELR_Hyp(uint32_t elr_hyp) +{ +__ASM volatile ("MSR elr_hyp, %0" : : "r" (elr_hyp) : "memory"); +} + +/** \brief Get SPSR Hypervisor Register + \return SPSR Hypervisor Register value + */ +__STATIC_FORCEINLINE uint32_t __get_SPSR_Hyp(void) +{ + uint32_t result; + __ASM volatile("MRS %0, spsr_hyp" : "=r" (result) ); + return(result); +} + +/** \brief Set SPSR Hypervisor Register + \param [in] spsr SPSR value to set + */ +__STATIC_FORCEINLINE void __set_SPSR_Hyp(uint32_t spsr) +{ +__ASM volatile ("MSR spsr_hyp, %0" : : "r" (spsr) : "memory"); +} + +/** \brief Get SPSR Register + \return SPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_SPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, spsr" : "=r" (result) ); + return(result); +} + +/** \brief Set SPSR Register + \param [in] spsr SPSR value to set + */ +__STATIC_FORCEINLINE void __set_SPSR(uint32_t spsr) +{ +__ASM volatile ("MSR cpsr, %0" : : "r" (spsr) : "memory"); +} + +/** \brief Get CPSR Register + \return CPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CPSR(void) +{ + uint32_t result; + __ASM volatile("MRS %0, cpsr" : "=r" (result) ); + return(result); +} + +/** \brief Set CPSR Register + \param [in] cpsr CPSR value to set + */ +__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr) +{ +__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory"); +} + +/** \brief Get Mode + \return Processor Mode + */ +__STATIC_FORCEINLINE uint32_t __get_mode(void) +{ + return (__get_CPSR() & 0x1FU); +} + +/** \brief Set Mode + \param [in] mode Mode value to set + */ +__STATIC_FORCEINLINE void __set_mode(uint32_t mode) +{ + __ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP(void) +{ + uint32_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint32_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + +/** \brief Get USR/SYS Stack Pointer + \return USR/SYS Stack Pointer value + */ +__STATIC_FORCEINLINE uint32_t __get_SP_usr(void) +{ + uint32_t cpsr = __get_CPSR(); + uint32_t result; + __ASM volatile( + "CPS #0x1F \n" + "MOV %0, sp " : "=r"(result) : : "memory" + ); + __set_CPSR(cpsr); + __ISB(); + return result; +} + +/** \brief Set USR/SYS Stack Pointer + \param [in] topOfProcStack USR/SYS Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack) +{ + uint32_t cpsr = __get_CPSR(); + __ASM volatile( + "CPS #0x1F \n" + "MOV sp, %0 " : : "r" (topOfProcStack) : "memory" + ); + __set_CPSR(cpsr); + __ISB(); +} + + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + //Permit access to VFP/NEON, registers by modifying CPACR + " MRC p15,0,R1,c1,c0,2 \n" + " ORR R1,R1,#0x00F00000 \n" + " MCR p15,0,R1,c1,c0,2 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB \n" + + //Enable VFP/NEON + " VMRS R1,FPEXC \n" + " ORR R1,R1,#0x40000000 \n" + " VMSR FPEXC,R1 \n" + + //Initialise VFP/NEON registers to 0 + " MOV R2,#0 \n" + + //Initialise D16 registers to 0 + " VMOV D0, R2,R2 \n" + " VMOV D1, R2,R2 \n" + " VMOV D2, R2,R2 \n" + " VMOV D3, R2,R2 \n" + " VMOV D4, R2,R2 \n" + " VMOV D5, R2,R2 \n" + " VMOV D6, R2,R2 \n" + " VMOV D7, R2,R2 \n" + " VMOV D8, R2,R2 \n" + " VMOV D9, R2,R2 \n" + " VMOV D10,R2,R2 \n" + " VMOV D11,R2,R2 \n" + " VMOV D12,R2,R2 \n" + " VMOV D13,R2,R2 \n" + " VMOV D14,R2,R2 \n" + " VMOV D15,R2,R2 \n" + +#if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + //Initialise D32 registers to 0 + " VMOV D16,R2,R2 \n" + " VMOV D17,R2,R2 \n" + " VMOV D18,R2,R2 \n" + " VMOV D19,R2,R2 \n" + " VMOV D20,R2,R2 \n" + " VMOV D21,R2,R2 \n" + " VMOV D22,R2,R2 \n" + " VMOV D23,R2,R2 \n" + " VMOV D24,R2,R2 \n" + " VMOV D25,R2,R2 \n" + " VMOV D26,R2,R2 \n" + " VMOV D27,R2,R2 \n" + " VMOV D28,R2,R2 \n" + " VMOV D29,R2,R2 \n" + " VMOV D30,R2,R2 \n" + " VMOV D31,R2,R2 \n" +#endif + + //Initialise FPSCR to a known state + " VMRS R1,FPSCR \n" + " LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero. + " AND R1,R1,R2 \n" + " VMSR FPSCR,R1 " + : : : "cc", "r1", "r2" + ); +} + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/CMSIS/Core_R/Include/cmsis_version.h b/CMSIS/Core_R/Include/cmsis_version.h new file mode 100644 index 0000000000..7d8fc2c715 --- /dev/null +++ b/CMSIS/Core_R/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(R) Version definitions + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 1U) /*!< [31:16] CMSIS Core(R) main version */ +#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(R) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(R) version number */ +#endif diff --git a/CMSIS/Core_R/Include/core_cr52.h b/CMSIS/Core_R/Include/core_cr52.h new file mode 100644 index 0000000000..798912bda9 --- /dev/null +++ b/CMSIS/Core_R/Include/core_cr52.h @@ -0,0 +1,387 @@ +/**************************************************************************//** + * @file core_cr52.h + * @brief CMSIS Cortex-R52 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CR52_H_GENERIC +#define __CORE_CR52_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_R52 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CR52 definitions */ +#define __CR52_CMSIS_VERSION_MAIN (1U) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CR52_CMSIS_VERSION_SUB (0U) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CR52_CMSIS_VERSION ((__CR52_CMSIS_VERSION_MAIN << 16U) | \ + __CR52_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_R (52U) /*!< Cortex-R Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if (defined(__ARM_NEON) && (__ARM_NEON == 1)) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CR52_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CR52_H_DEPENDANT +#define __CORE_CR52_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + + /* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CR52_REV + #define __CR52_REV 0x0000U + #warning "__CR52_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ECC_PRESENT + #define __ECC_PRESENT 0U + #warning "__ECC_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas + +/*@} end of group Cortex_R52 */ + + + + /******************************************************************************* + * Register Abstraction + Core Register contain: + - CPSR + ******************************************************************************/ + +/* Core Register CPSR */ +typedef union +{ + struct + { + uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */ + uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */ + uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */ + uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */ + uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ + uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */ + uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ + RESERVED(0:4, uint32_t) + uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */ + uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */ + uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPSR_Type; + + + +/* CPSR Register Definitions */ +#define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ +#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ + +#define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */ +#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */ + +#define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */ +#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */ + +#define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */ +#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */ + +#define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */ +#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */ + +#define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */ +#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */ + +#define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */ +#define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */ + +#define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */ +#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */ + +#define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */ +#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */ + +#define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */ +#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */ + +#define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */ +#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */ + +#define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */ +#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */ + +#define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */ +#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */ + +#define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */ +#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */ + +#define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ +#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ + +#define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */ +#define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */ +#define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */ +#define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */ +#define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */ +#define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */ +#define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */ +#define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ +#define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CR52_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Device/ARM/ARMCR52/Include/ARMCR52.h b/Device/ARM/ARMCR52/Include/ARMCR52.h new file mode 100644 index 0000000000..77ddd7f8c5 --- /dev/null +++ b/Device/ARM/ARMCR52/Include/ARMCR52.h @@ -0,0 +1,105 @@ +/****************************************************************************** + * @file ARMCR52.h + * @brief CMSIS Core Peripheral Access Layer Header File for + * ARMCR52 Device + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARMCR52_H +#define ARMCR52_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of Core Peripherals ----------------------------------- */ +#define __CR52_REV 0x0101U /* Core revision r1p1 */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 0U /* no FPU present */ +#define __FPU_DP 0U /* single precision FPU */ +#define __DSP_PRESENT 0U /* no DSP extension present */ +#define __ICACHE_PRESENT 1U /* Instruction cache present */ +#define __DCACHE_PRESENT 1U /* Data cache present */ +#define __DTCM_PRESENT 1U /* Tightly-Coupled Memory present */ +#define __ECC_PRESENT 1U /* Memory with Error Correcting Code */ + +#include "core_cr52.h" /* Processor and core peripherals */ +#include "system_ARMCR52.h" /* System Header */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* ARMCR52_H */ diff --git a/Device/ARM/ARMCR52/Include/ARMCR52_DSP_DP_FP.h b/Device/ARM/ARMCR52/Include/ARMCR52_DSP_DP_FP.h new file mode 100644 index 0000000000..a7b266fe25 --- /dev/null +++ b/Device/ARM/ARMCR52/Include/ARMCR52_DSP_DP_FP.h @@ -0,0 +1,105 @@ +/****************************************************************************** + * @file ARMCR52_DSP_DP_FP.h + * @brief CMSIS Core Peripheral Access Layer Header File for + * ARMCR52 Device + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARMCR52_DSP_DP_FP_H +#define ARMCR52_DSP_DP_FP_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of Core Peripherals ----------------------------------- */ +#define __CR52_REV 0x0101U /* Core revision r1p1 */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __FPU_DP 1U /* double precision FPU */ +#define __DSP_PRESENT 1U /* DSP extension present */ +#define __ICACHE_PRESENT 1U /* Instruction cache present */ +#define __DCACHE_PRESENT 1U /* Data cache present */ +#define __DTCM_PRESENT 1U /* Tightly-Coupled Memory present */ +#define __ECC_PRESENT 1U /* Memory with Error Correcting Code */ + +#include "core_cr52.h" /* Processor and core peripherals */ +#include "system_ARMCR52.h" /* System Header */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* ARMCR52_DSP_DP_FP_H */ diff --git a/Device/ARM/ARMCR52/Include/ARMCR52_FP.h b/Device/ARM/ARMCR52/Include/ARMCR52_FP.h new file mode 100644 index 0000000000..d693db79f9 --- /dev/null +++ b/Device/ARM/ARMCR52/Include/ARMCR52_FP.h @@ -0,0 +1,105 @@ +/****************************************************************************** + * @file ARMCR52_FP.h + * @brief CMSIS Core Peripheral Access Layer Header File for + * ARMCR52 Device + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ARMCR52_FP_H +#define ARMCR52_FP_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of Core Peripherals ----------------------------------- */ +#define __CR52_REV 0x0101U /* Core revision r1p1 */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __FPU_DP 0U /* single precision FPU */ +#define __DSP_PRESENT 0U /* no DSP extension present */ +#define __ICACHE_PRESENT 1U /* Instruction cache present */ +#define __DCACHE_PRESENT 1U /* Data cache present */ +#define __DTCM_PRESENT 1U /* Tightly-Coupled Memory present */ +#define __ECC_PRESENT 1U /* Memory with Error Correcting Code */ + +#include "core_cr52.h" /* Processor and core peripherals */ +#include "system_ARMCR52.h" /* System Header */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* ARMCR52_FP_H */ diff --git a/Device/ARM/ARMCR52/Include/system_ARMCR52.h b/Device/ARM/ARMCR52/Include/system_ARMCR52.h new file mode 100644 index 0000000000..ed48ad66c4 --- /dev/null +++ b/Device/ARM/ARMCR52/Include/system_ARMCR52.h @@ -0,0 +1,57 @@ +/**************************************************************************//** + * @file system_ARMCR52.h + * @brief CMSIS Device System Header File for + * ARMCR52 Device + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SYSTEM_ARMCR52_H +#define SYSTEM_ARMCR52_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_ARMCR52_H */ diff --git a/Device/ARM/ARMCR52/Source/GCC/gcc_arm.ld b/Device/ARM/ARMCR52/Source/GCC/gcc_arm.ld new file mode 100644 index 0000000000..9f825eb5af --- /dev/null +++ b/Device/ARM/ARMCR52/Source/GCC/gcc_arm.ld @@ -0,0 +1,371 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-R based device + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- + Flash Configuration + Flash Base Address <0x0-0xFFFFFFFF:8> + Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- + RAM Configuration + RAM Base Address <0x0-0xFFFFFFFF:8> + RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- + Stack / Heap Configuration + Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/*--------------------- EL2 Stack Configuration ----------------------- + EL2 Stack Configuration + Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__EL2_STACK_SIZE = 0x00000100; + + +/* + *-------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE + TCMA (rw) : ORIGIN = 0x40000000, LENGTH = 0x8000 + TCMB (rw) : ORIGIN = 0x40100000, LENGTH = 0x8000 + TCMC (rw) : ORIGIN = 0x40200000, LENGTH = 0x8000 +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __ecc_table_start__ + * __ecc_table_end__ + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __EL2StackLimit + * __EL2StackTop + */ +ENTRY(__EL2_Vectors) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option �--section-start� or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + + /* ECC initialization is done by 64-bit writes thus used symbols + * must be 8byte aligned */ + .ecc.table : + { + . = ALIGN(8); + __ecc_table_start__ = .; + + QUAD (__bss_start__) + QUAD ((__bss_end__ - __bss_start__) / 8) + +/* + QUAD (__bss2_start__) + QUAD ((__bss2_end__ - __bss2_start__) / 8) +*/ + + QUAD (__HeapTop) + QUAD ((__HeapLimit - __HeapTop) / 8) + + QUAD (__StackLimit) + QUAD ((__StackLimit - __StackTop) / 8) + + QUAD (__EL2StackLimit) + QUAD ((__EL2StackLimit - __EL2StackTop) / 8) + + QUAD (__TCMA_Start) + QUAD ((__TCMA_Start + __TCMA_Length) / 8) + + QUAD (__TCMB_Start) + QUAD ((__TCMB_Start + __TCMB_Length) / 8) + + QUAD (__TCMC_Start) + QUAD ((__TCMC_Start + __TCMC_Length) / 8) + + __ecc_table_end__ = .; + } > FLASH + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + /** + * Location counter can end up 2byte aligned with narrow Thumb code but + * __etext is assumed by startup code to be the LMA of a section in RAM + * which must be 4byte aligned + */ + __etext = ALIGN (8); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table and .ecc.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (4); + + .data2 : AT (__etext2) + { + . = ALIGN(8); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(8); + __data2_end__ = .; + + } > RAM2 +*/ + + /* Due ECC initialization sequence __bss_start__ and __bss_end__ must be aligned on 8 bytes */ + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table and .ecc.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(8); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(8); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + /* Due ECC initialization sequence __bss_start__ and __bss_end__ must be aligned on 8 bytes */ + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + __HeapTop = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM AT > RAM + + /* Due ECC initialization sequence __StackLimit and __StackTop should be aligned on 8 bytes */ + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __EL2_STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + + /* Set EL2 stack top to end of RAM. Then set regular stack top, + * and stack limit move down by size of __STACK_SIZE section */ + /* Due ECC initialization sequence __EL2StackLimit and __EL2StackTop msut be aligned on 8 bytes */ + .el2_stack (ORIGIN(RAM) + LENGTH(RAM) - __EL2_STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __EL2StackLimit = .; + . = . + __EL2_STACK_SIZE; + . = ALIGN(8); + __EL2StackTop = .; + } > RAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack + EL2stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + __TCMA_Start = ORIGIN(TCMA); + __TCMA_Length = LENGTH(TCMA); + __TCMB_Start = ORIGIN(TCMB); + __TCMB_Length = LENGTH(TCMB); + __TCMC_Start = ORIGIN(TCMC); + __TCMC_Length = LENGTH(TCMC); +} diff --git a/Device/ARM/ARMCR52/Source/GCC/startup_ARMCR52.c b/Device/ARM/ARMCR52/Source/GCC/startup_ARMCR52.c new file mode 100644 index 0000000000..793f15f613 --- /dev/null +++ b/Device/ARM/ARMCR52/Source/GCC/startup_ARMCR52.c @@ -0,0 +1,158 @@ +/****************************************************************************** + * @file startup_ARMCR52.c + * @brief CMSIS Core Device Startup File for Cortex-R52 Device + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCR52) + #include "ARMCR52.h" +#elif defined (ARMCR52_FP) + #include "ARMCR52_FP.h" +#elif defined (ARMCR52_DSP_DP_FP) + #include "ARMCR52_DSP_DP_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void EL2_Default_Handler(void); +void EL1_Default_Handler(void); +void __NAKED __NO_RETURN EL2_Reset_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +void EL2_Undef_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void EL2_SVC_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void EL2_Prefetch_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void EL2_Abort_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void EL2_Reserved_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void EL2_IRQ_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void EL2_FIQ_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); + +void EL1_Reset_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void EL1_Undef_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void EL1_SVC_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void EL1_Prefetch_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void EL1_Abort_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void EL1_Reserved_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void EL1_IRQ_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void EL1_FIQ_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +void __VECTOR_TABLE_ATTRIBUTE __VECTOR_TABLE_EL2(void) +{ + __ASM volatile( + "LDR PC,=EL2_Reset_Handler \n" + "B.W EL2_Undef_Handler \n" + "B.W EL2_SVC_Handler \n" + "B.W EL2_Prefetch_Handler \n" + "B.W EL2_Abort_Handler \n" + "B.W EL2_Reserved_Handler \n" + "B.W EL2_IRQ_Handler \n" + "B.W EL2_FIQ_Handler \n" + ); +} + +void __VECTOR_TABLE_ATTRIBUTE __VECTOR_TABLE_EL1(void) +{ + __ASM volatile( + "B.W EL1_Reset_Handler \n" + "B.W EL1_Undef_Handler \n" + "B.W EL1_SVC_Handler \n" + "B.W EL1_Prefetch_Handler \n" + "B.W EL1_Abort_Handler \n" + "B.W EL1_Reserved_Handler \n" + "B.W EL1_IRQ_Handler \n" + "B.W EL1_FIQ_Handler \n" + ); +} + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Switch from EL2 to EL1 mode + *----------------------------------------------------------------------------*/ +void __NAKED __NO_RETURN SwitchEL2toEL1(uint32_t func) +{ + register CPSR_Type spsr_hyp; + + __set_ELR_Hyp(func); + + spsr_hyp.w = __get_SPSR_Hyp(); +#if defined(__thumb2__) && (__thumb2__==1) + /* Thumb instruction set and supervisor mode */ + spsr_hyp.b.M = CPSR_M_SVC; + spsr_hyp.b.T = 1; +#else + /* ARM instruction set and supervisor mode */ + spsr_hyp.b.M = CPSR_M_SVC; +#endif + __set_SPSR_Hyp(spsr_hyp.w); + + __ERET(); + +} + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void __NAKED __NO_RETURN EL2_Reset_Handler(void) +{ + __EARLY_INIT(); + __set_SP((uint32_t)&__INITIAL_SP); + SystemInit(); /* CMSIS System Initialization */ + + /* ARMv8-R cores are in EL2 (hypervisor mode) after reset, and we need + to first descend to EL1 (supervisor mode) before the traditional SP + setting code can be run */ + SwitchEL2toEL1((uint32_t)&__PROGRAM_START); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void EL2_Default_Handler(void) +{ + while(1); +} + +void EL1_Default_Handler(void) +{ + while(1); +} diff --git a/Device/ARM/ARMCR52/Source/system_ARMCR52.c b/Device/ARM/ARMCR52/Source/system_ARMCR52.c new file mode 100644 index 0000000000..1526168742 --- /dev/null +++ b/Device/ARM/ARMCR52/Source/system_ARMCR52.c @@ -0,0 +1,109 @@ +/**************************************************************************//** + * @file system_ARMCR52.c + * @brief CMSIS Device System Source File for + * ARMCR52 Device + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCR52) + #include "ARMCR52.h" +#elif defined (ARMCR52_FP) + #include "ARMCR52_FP.h" +#elif defined (ARMCR52_DSP_DP_FP) + #include "ARMCR52_DSP_DP_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define XTAL (50000000UL) /* Oscillator frequency */ + +#define SYSTEM_CLOCK (XTAL / 2U) + + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __VECTOR_TABLE_EL2; +extern uint32_t __VECTOR_TABLE_EL1; + +extern void TcmInit(void); + + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + uint32_t ctrl; + + __set_HVBAR((uint32_t)&__VECTOR_TABLE_EL2); + __set_VBAR((uint32_t)&__VECTOR_TABLE_EL1); + +#if defined (__DTCM_PRESENT) && (__DTCM_PRESENT == 1U) + /* TCM initialization */ + TcmInit(); +#endif + + /* I-cache & D-cache initialization */ + /* EL2 */ + ctrl = __get_HSCTLR(); +#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + ctrl |= 0x1000; /* Set I bit */ +#endif +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + ctrl |= 0x0004; /* Set C bit */ +#endif + __set_HSCTLR(ctrl); + + /* EL1/0 */ + ctrl = __get_SCTLR(); +#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + ctrl |= 0x1000; /* Set I bit */ +#endif +#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + ctrl |= 0x0004; /* Set C bit */ +#endif + __set_SCTLR(ctrl); + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + // Enable FPU + __FPU_Enable(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/Device/ARM/ARMCR52/Source/tcm_init.c b/Device/ARM/ARMCR52/Source/tcm_init.c new file mode 100644 index 0000000000..14419facbb --- /dev/null +++ b/Device/ARM/ARMCR52/Source/tcm_init.c @@ -0,0 +1,66 @@ +/**************************************************************************//** + * @file tcm_init.c + * @brief TCM initialization functions for + * ARMCR52 Device + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCR52) + #include "ARMCR52.h" +#elif defined (ARMCR52_FP) + #include "ARMCR52_FP.h" +#elif defined (ARMCR52_DSP_DP_FP) + #include "ARMCR52_DSP_DP_FP.h" +#else + #error device not specified! +#endif + + +#define TCM_BASEADDR_MASK 0xFFFFE000 +#define TCM_ENABLEEL10 (0x1 << 0) +#define TCM_ENABLEEL2 (0x1 << 1) +#define TCM_SIZE_32KB (0x6 << 2) + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __TCMA_Start, __TCMB_Start, __TCMC_Start; + +/*---------------------------------------------------------------------------- + TCM initialization + *----------------------------------------------------------------------------*/ +void TcmInit(void) +{ + uint32_t config; + + config = ((uint32_t)&__TCMA_Start)&TCM_BASEADDR_MASK; + config |= TCM_SIZE_32KB|TCM_ENABLEEL2|TCM_ENABLEEL10; /* 32k; EL0/1=ON L2=ON */ + __set_IMP_ATCMREGIONR(config); /* Write to A-TCM config reg */ + + config = ((uint32_t)&__TCMB_Start)&TCM_BASEADDR_MASK; + config |= TCM_SIZE_32KB|TCM_ENABLEEL2|TCM_ENABLEEL10; /* 32k; EL0/1=ON L2=ON */ + __set_IMP_BTCMREGIONR(config); /* Write to B-TCM config reg */ + + config = ((uint32_t)&__TCMC_Start)&TCM_BASEADDR_MASK; + config |= TCM_SIZE_32KB|TCM_ENABLEEL2|TCM_ENABLEEL10; /* 32k; EL0/1=ON L2=ON */ + __set_IMP_CTCMREGIONR(config); /* Write to B-TCM config reg */ +} +